Journals
2024
[1] K. Xu, X. Kong and R. B. Staszewski, “An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-II), vol. x, iss. x, pp. x–x, xxx. 2024. DOI: 10.1109/TC- SII.2022.3231568. [IEEE Xplore link (Open Access)]
2023
[1] J. Anders, M. Babaie, J. Bardin, I. Bashir, G. Billiot, E. Blokhina, S. Bonen, E. Charbon, J. Chiaverini, I.L Chuang, C. Degenhardt, D. Englund, L. Geck, L.L. Guevel, D. Ham, R. Han, M. Ibrahim, D. Krueger, K.M Lei, A. Morel, D. Nielinger, G. Pillonnet, J. Sage, F. Sebastiano, R.B. Staszewski, J. Stuart, A. Vladimirescu, P. Vliex, S.P. Voinigescu, “CMOS integrated circuits for the quantum information sciences”, IEEE Trans. on Quantum Engineering (TQE), vol. 4, pp. 1–30, 28 Sept. 2023. DOI: 10.1109/TQE.2023.3290593. [IEEE Xplore link (Open Access)]
[2] Z. Gao, M. Fritz, G. Spalink, R. B. Staszewski and M. Babaie, “A Digital PLL-Based Phase Modulator with Non-Uniform Clock Compensation and Nonlinearity Predistortion” IEEE Journal of Solid-State Circuits (JSSC), vol. 58, iss. 9, pp. 2526–2542, Sept. 2023. DOI: 10.1109/JSSC.2023.3270265. [IEEE Xplore link (Open Access)] (pre-published)
[3] X. Chen, Y. Hu, T. Siriburanon, J. Du, R. B. Staszewski and A. Zhu, “A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness”, IEEE Journal of Solid-State Circuits (JSSC), vol. 58, iss. 7, pp. 1945–1958, Jul. 2023. DOI: 10.1109/JSSC.2023.3237788. [IEEE Xplore link (Open Access)] (pre-published)
[4] A. Esmailiyan, E. Blokhina, D. M. Andrade Miceli, E. Faust, P. Giounanlis, D. Leipold, H. Wang, I. Bashir, E. Koskin, T. Siriburanon and R. B. Staszewski, “An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-II), vol. 70, iss. 6, pp. 1861–1865, Jun. 2023. DOI: 10.1109/TC- SII.2022.3231568. [IEEE Xplore link (Open Access)]
[5] Z. Gao, J. He, M. Fritz, J. Gong, Y. Shen, Z. Zong, P. Chen. G. Spalink, B. Eitel, M. Alavi, R. B. Staszewski and M. Babaie, “A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit”, IEEE Journal of Solid-State Circuits (JSSC), vol. 58, iss. 6, pp. 1552 - 1571, Jun. 2023. DOI: 10.1109/JSSC.2022.3209338. [IEEE Xplore link (Open Access)]
2022
[1] V. Nguyen, F. Schembari and R. B. Staszewski, “Exploring Speed Maximization of Frequency-to-Digital Conversion for Ultra- Low-Voltage VCO-Based ADCs”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 70, iss. 3, pp. 1–14, 1043–1056, Mar. 2022. DOI: 10.1109/TCSI.2022.3223468. [IEEE Xplore link (Open Access)]
[2] E. Kobal, T. Siriburanon, R. B. Staszewski and A. Zhu, “A Compact, Low-Power, Low-NF, Millimeter-Wave Cascode LNA With Magnetic Coupling Feedback in 22-nm FD-SOI CMOS for 5G Applications”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 70, iss. 4, 1331–1335, Apr. 2022. DOI: 10.1109/TCSII.2022.3224412. [IEEE Xplore link (Open Access)]
[3] H. M. Nguyen, F. Zhang, I. O’Connell, R. B. Staszewski and J. S. Walling, “An Edge-Combining, Frequency Multiplying Class-D Power Amplifier”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 70, iss. 2, pp. 471–475, Feb. 2023. DOI: 10.1109/TC- SII.2022.3171495. [IEEE Xplore link (Open Access)]
[4] E. Kobal, T. Siriburanon, X. Chen, H. M. Nguyen, R. B. Staszewski and A. Zhu, “A Gm-Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 12, iss. 1, pp. 5007–5017, Dec. 2022. DOI: 10.1109/TCSI.2022.3200161. [IEEE Xplore link (Open Access)]
[5] R. B. Staszewski, A. Esmailiyan, H. Wang, E. Koskin, P. Giounanlis, X. Wu, A. Koziol, A. Sokolov, I. Bashir, M. Asker, D. Leipold, R. Nikandish, T. Siriburanon and E. Blokhina, “Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC”, IEEE Open Journal of Solid-State Circuits Society (OJ-SSCS), vol. 2, pp. 103–121, 10 Oct. 2022. DOI: 10.1109/OJSSCS.2022.3213528. [IEEE Xplore link (Open Access)]
[6] S. Binsfeld Ferreira, F Baumgratz, S. Bampi and R. B. Staszewski, “Design of High-IF Discrete-time Receivers for IoT: Demystifying Aliasing Trade-offs”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 69, iss. 7, pp. 3078–3083, Jul. 2022. DOI:10.1109/TCSII.2022.3175431. [IEEE Xplore link (Open Access)]
[7] Y. Hu, T. Siriburanon and R. B. Staszewski, “Multirate Timestamp Modeling for Ultra-Low-Jitter Frequency Synthesis: A Tutorial”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 69, iss. 7, pp. 3030–3036, Jul. 2022. DOI: 10.1109/TCSII.2022.3171498. [IEEE Xplore link (Open Access)]
[8] A. Bozorg and R. B. Staszewski, “A Charge-Rotating IIR Filter with Linear Interpolation and High Stop-Band Rejection” , IEEE Journal of Solid-State Circuits (JSSC ), vol. 57, iss. 7, pp. 2091–2101, Jul. 2022. DOI: 10.1109/JSSC.2022.3166960. [IEEE Xplorelink (Open Access)]
[9] Y. Chen, J. Gong, R. B. Staszewski and M. Babaie, “A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and ‹-54 dBc Spurs Under 50-mVpp Supply Ripple”, IEEE Journal of Solid-State Circuits (JSSC), vol. 57, iss. 6, pp. 1749–1764, Jun. 2021. DOI: 10.1109/JSSC.2021.3123386. [IEEE Xplore link (Open Access)]
[10] V. Nguyen, F. Schembari and R. B. Staszewski, “A deep-subthreshold variation-aware 0.2 V open-loop VCO-based ADC” ,IEEE Journal of Solid-State Circuits (JSSC), vol. 57, iss. 6, pp. 1684–1699, Jun. 2022. DOI: 10.1109/JSSC.2021.3114006. [IEEE Xplore link (Open Access)]
[11] H. M. Nguyen, J. S. Walling, A. Zhu and R. B. Staszewski, “A mm-Wave switched-capacitor RFDAC” ,IEEE Journal of Solid- State Circuits (JSSC), vol. 57, iss. 4, pp. 1224–1238, Apr. 2022. DOI: 10.1109/JSSC.2022.3142718. [IEEE Xplore link (Open Access)]
[12] X. Chen, Y. Hu, T. Siriburanon, J. Du, R. B. Staszewski and A. Zhu, “Flicker Phase Noise Reduction Using Gate–Drain Phase Shift in Transformer-Based Oscillators” , IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 69, iss. 3, pp. 973–984, Mar. 2022. DOI: 10.1109/TCSI.2021.3131968. [IEEE Xplore link (Open Access)]
[13] Y. Hu, X. Chen, T Siriburanon, J. Du, V. Govindaraj, A. Zhu and R. B. Staszewski, “A charge-sharing locking technique with a general phase noise theory of injection locking” , IEEE Journal of Solid-State Circuits (JSSC), vol. 57, iss. 2, pp. 518–534, Feb. 2022. DOI: 10.1109/JSSC.2021.3106237. [IEEE Xplore link (Open Access)]
[14] J. Du, Y. Hu, T. Siriburanon, E. Kobal, P. Quinlan A. Zhu and R. B. Staszewski, “A compact 0.2–0.3-V inverse-class-F23 oscillator for low 1/f3 noise over wide tuning range” ,IEEE Journal of Solid-State Circuits (JSSC), vol. 57, iss. 2, pp. 452–464, Feb. 2022. DOI: 10.1109/JSSC.2021.3098770. [IEEE Xplore link (Open Access)]
[15] P. Chen, J. Yin, F. Zhang, P.-I. Mak, R. P. Martins and R. B. Staszewski, “Mismatch analysis of DTCs with an improved BIST-TDC in 28-nm CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 69, iss. 1, pp. 51–63, Jan. 2022. DOI: 10.1109/TCSI.2021.3105451. [IEEE Xplore link (Open Access)]
[16] P. Chen, X. Meng, J. Yin, P.-I. Mak, R. P. Martins and R. B. Staszewski, “A 529–µW fractional-N all-digital PLL using TDC gain auto-calibration and an inverse-class-F DCO in 65-nm CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 69, iss. 1, pp. 1–13, Jan. 2022. DOI: 10.1109/TCSI.2021.3094094. [IEEE Xplore link (Open Access)]
[17] A. Bozorg and R. B. Staszewski, “A 20 MHz–2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 69, iss. 1, pp. 42–50, Jan. 2022. DOI: 10.1109/TCSI.2021.3092960. [IEEE Xplore link (Open Access)]
[18] G. R. Nikandish, A. Nasri, A.Yousefi, A.Zhu and R. B. Staszewski, “A broadband fully integrated power amplifier using waveform shaping multi-resonance harmonic matching network”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 69, iss. 1, pp. 2–15, Jan. 2022. DOI: 10.1109/TCSI.2021.3095708. [IEEE Xplore link (Open Access)]
[19] A. Bozorg and R. B. Staszewski, “A clock-phase reuse technique for discrete-time band-pass filters”, IEEE Journal of Solid-State Circuits (JSSC), vol. 57, iss. 1, pp. 290–231, Jan. 2022. DOI: 10.1109/JSSC.2021.3086621. [IEEE Xplore link (Open Access)]
[A1] S. Hu, P. Chen, P. Quinlan and R. B. Staszewski, “A Novel Waveform-Tracking BLE Receiver”, TechRxiv Preprint, vol. 68, iss. 6, pp. 1–5, 11 Mar. 2022. DOI: https://dx.doi.org/10.36227/techrxiv.19342376.v1. [TechRxiv Preprint link]
2021
[1] Y. Fang, R. B. Staszewski and H. Gao, “Three-Winding Transformer-Based 60-GHz DCO with -185.1 dB FoM in 40-nm CMOS”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 99, iss. x, pp. xx–xx, 21 Dec. 2021. DOI: 10.1109/LSSC.2021.3137131. [IEEE Xplore link]
[2] X. Chen, Y. Hu, T. Siriburanon, J. Du, R. B. Staszewski and A. Zhu, “Flicker Phase Noise Reduction Using Gate–Drain Phase Shift in Transformer-Based Oscillators”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 99, pp. 1–12, 7 Dec. 2021. DOI: 10.1109/TCSI.2021.3131968. [IEEE Xplore link (Open Access)]
[3] Y. Chen, J. Gong, R. B. Staszewski and M. Babaie, “A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and ‹-54 dBc Spurs Under 50-mVpp Supply Ripple”, IEEE Journal of Solid-State Circuits (JSSC), vol. 57, iss. 6, pp. 1749–1764, Jun. 2021. DOI: 10.1109/JSSC.2021.3123386. [IEEE Xplore link (Open Access)]
[4] V. Nguyen, F. Schembari and R. B. Staszewski, “A Deep-Subthreshold Variation-Aware 0.2 V Open-Loop VCO-Based ADC”, IEEE Journal of Solid-State Circuits (JSSC), vol. 99, iss. x, pp. 1–14, 12 Oct. 2020. DOI: 10.1109/JSSC.2021.3114006. [IEEE Xplore link (Open Access)]
[5] Y. Hu, X. Chen, T. Siriburanon, J. Du, V. Govindaraj, A. Zhu and R. B. Staszewski, “A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking”, IEEE Journal of Solid-State Circuits (JSSC), vol. 99, pp. 1–16, 06 Sept. 2021. DOI: 10.1109/JSSC.2021.3106237. [IEEE Xplore link (Open Access)]
[6] P. Chen, J. Yin, F. Zhang, P.-I. Mak, R. P. Martins and R. B. Staszewski, “Mismatch Analysis of DTCs with an Improved BIST-TDC in 28-nm CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 99, iss. xx pp. 1–11, 27 Aug. 2021. DOI: 10.1109/TCSI.2021.3105451. [IEEE Xplore link (Open Access)]
[7] J. Du, Y. Hu, T. Siriburanon, E. Kobal, P. Quinlan, A. Zhu and R. B. Staszewski, “A Compact 0.2–0.3-V Inverse-Class-F23 Oscillator for Low 1/f3 Noise over Wide Tuning Range”, IEEE Journal of Solid-State Circuits (JSSC), vol. 99, pp. 1–14, 02 Aug. 2021. DOI: 10.1109/JSSC.2021.3098770. [IEEE Xplore link (Open Access)]
[8] P. Chen, X. Meng, J. Yin, P.-I. Mak, R. P. Martins and R. B. Staszewski, “A 529–µW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 99, iss. xx pp. 1–13, 26 Jul. 2021. DOI: 10.1109/TCSI.2021.3094094. [IEEE Xplore link (Open Access)]
[9] G. R. Nikandish, A. Nasri, A. Yousefi, A. Zhu and R. B. Staszewski, “A Broadband Fully Integrated Power Amplifier Using Waveform Shaping Multi-Resonance Harmonic Matching Network”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 99, iss. x, pp. 1–14, 14 Jul. 2021. DOI: 10.1109/TCSI.2021.3095708. [IEEE Xplore link (Open Access)]
[10] G. Nikandish, E. Blokhina, D. Leipold and R. B. Staszewski, “Semiconductor Quantum Computing: Toward a CMOS Quantum Computer on Chip”, IEEE Nanotechnology Magazine (INM), vol. 15, iss. 6, pp. 8–20, Dec. 2021. DOI:10.1109/MNANO.2021.3113216. [IEEE Xplore link]
[11] T.-H. Tsai, R.-B. Sheen, S.-Y. Hsu, C.-H. Chang and R. B. Staszewski, “A 55.9-fs Integrated Jitter (100 kHz to 100 MHz) Hybrid LC-tank PLL in 5-nm FinFET using Programmable Phase Re-alignment and Dynamic Coarse Tuning”, IEEE Solid-State Circuits Letters (SSC-L), vol. 4, pp. 230–233, 25 Nov. 2021. DOI: 10.1109/LSSC.2021.3130575. [IEEE Xplore link (Open Access)
[12] J. Du, T. Siriburanon, X. Chen, Y. Hu, V. Govindaraj, A. Zhu and R. B. Staszewski, “A Millimeter-Wave ADPLL with Refer- ence Oversampling and Third-Harmonic Extraction Featuring High FoMjitter-N”, IEEE Solid-State Circuits Letters (SSCL), vol. 4, pp. 214–217, 29 Oct. 2021. DOI: 10.1109/LSSC.2021.3124130. [IEEE Xplore link (Open Access)]
[13] E. Blokhina, A. Sokolov, P. Giounanlis, X. Wu, I. Bashir, D. Leipold, R. B. Staszewski, A. Brambilla and F. Bizzarri, “Towards the Co-Simulation of Charge Qubits: a Methodology Grounding on an Equivalent Circuit Representation”, IEEE Open Journal of Circuits and Systems (OJCAS), vol. 2, pp. 548-563, 13 Sept. 2021. DOI: 10.1109/OJCAS.2021.3105005. [IEEE Xplore link (Open Access)]
[14] J. Du, T. Siriburanon, Y. Hu, V. Govindaraj and R. B. Staszewski, “A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL”, IEEE Journal of Solid-State Circuits (JSSC), vol. 56, iss. 11, pp. 3445–3457, Nov. 2021. DOI:10.1109/JSSC.2021.3101046. [IEEE Xplore link (Open Access)]
[15] H. Ghaedrahmati, J. Zhou and R. B. Staszewski, “A 38.6-fJ/Conv.-Step Inverter-Based Continuous-Time Bandpass ΔΣ ADC in 28 nm Using Asynchronous SAR Quantizer”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 68 iss. 9, pp. 3113–3117, Sept. 2021. DOI: 10.1109/TCSII.2021.3089831. [IEEE Xplore link (Open Access)]
[16] P. Giounanlis, X. Wu, D. Leipold, A. Sokolov, E. Koskin, N. Petropoulos, I. Bashir, R. B. Staszewski and E. Blokhina, “CMOS charge qubits and qudits: Entanglement entropy and mutual information as an optimization method to construct CNOT and SWAP gates”, IOP Science – Semiconductor Science and Technology, vol. 36, no. 9, pp. 1–15, 30 Jul. 2021. DOI: 10.1088/1361- 6641/abe550. [IOP link (journal link)] [IOP link (Open Access)]
[17] R. B. Staszewski, I. Bashir, E. Blokhina and D. Leipold, “Cryo-CMOS for quantum system on-chip integration: Quantum computing as the development driver”, IEEE Solid-State Circuits (SSC) Magazine, vol. 13, no. 2, pp. 46–53, Spring 2021. DOI: 10.1109/MSSC.2021.3072807. [IEEE Xplore link]
[18] M. Bagheri, F. Schembari, H. Zare-Hoseini, R. B. Staszewski and A. Nathan, “Interchannel mismatch calibration techniques for time-interleaved SAR ADCs”, IEEE Open Journal of Circuits and Systems (OJCAS), vol. 2, pp.420–433, 25 May. 2021. DOI: 10.1109/OJCAS.2021.3083680. [IEEE Xplore link (Open Access)]
[19] S. Hu, P. Chen, P. Quinlan and R. B. Staszewski, “A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 68, iss. 6, pp. 2317–2328, Jun. 2021. DOI: 10.1109/TCSI.2021.3070782. [IEEE Xplore link (Open Access)]
[20] M. A. Shehata, V. Roy, J. Breslin, H. Shanan, M. Keaveney and R. B. Staszewski, “A 32—42-GHz RTWO-Based Frequency Quadrupler Achieving ›37 dBc Harmonic Rejection in 22-nm FD-SOI”, IEEE Solid-State Circuits Letters (SSC-L), vol. 4, pp. 72– 75, Apr. 2021. DOI: 10.1109/LSSC.2021.3055628. [IEEE Xplore link (Open Access)]
[21] M. A. Shehata, M. Keaveney and R. B. Staszewski, “A distributed stubs technique to mitigate flicker noise upconversion in a mm-wave rotary traveling-wave oscillator”, IEEE Journal of Solid-State Circuits (JSSC), vol. 56, iss. 6, pp. 1745–1760, Jun. 2021. DOI: 10.1109/JSSC.2020.3044278. [IEEE Xplore link (Open Access)]
[22] C.-C. Li, M.-S. Yuan, C.-C. Liao, C.-H. Chang, Y.-T. Lin, T.-H. Tsai, T.-C. Huang, H.-Y. Liao, C.-T. Lu, H.-Y. Kuo, A. Ronchini Ximenes and R. B. Staszewski, “A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 68, iss. 5, pp. 1881–1891, May 2021. DOI: 10.1109/TCSI.2021.3059484. [IEEE Xplore link (Open Access)]
[23] F. Zhang, P. Chen, J. S. Walling, A. Zhu and R. B. Staszewski, “An active-under-coil RFDAC with analog linear interpolation in 28-nm CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-I), (accepted) vol. 68, iss. 5, pp. 1855–1868, May 2021. DOI: 10.1109/TCSI.2021.3059368. [IEEE Xplore link (Open Access)]
[24] A. Esmailiyan, J. Du, T. Siriburanon, F. Schembari and R. B. Staszewski, “Dickson-charge-pump-based voltage-to-time conver- sion for time-based ADCs in 28nm CMOS”, IEEE Open Journal of Circuits and Systems (OJCAS), vol. 2, pp. 23–31, 8 Jan. 2021. DOI: 10.1109/OJCAS.2020.3043094. [IEEE Xplore link (Open Access)]
[25] Y. Hu, T. Siriburanon and R. B. Staszewski, “Oscillator flicker phase noise: A tutorial”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 68, iss. 2 pp. 538–544, Feb. 2021. DOI: 10.1109/TCSII.2020.3043165. [IEEE Xplore link (Open Access)]
[26] A. Bozorg and R. B. Staszewski, “A 0.02–4.5-GHz LN(T)A in 28-nm CMOS for 5G exploiting noise reduction and current reuse”, IEEE Journal of Solid-State Circuits (JSSC), vol. 56, iss. 2, pp. 404–415, Feb. 2021. DOI: 10.1109/JSSC.2020.3018680. [IEEE Xplore link (Open Access)]
[27] G. Nikandish, R. B. Staszewski and A. Zhu, “Unbalanced power amplifier: An architecture for broadband backoff efficiency enhancement”, IEEE Journal of Solid-State Circuits (JSSC), vol. 56, iss. 2, pp. 367–381, Feb. 2021. DOI: 10.1109/JSSC.2020.3014244. [IEEE Xplore link]
[28] S. Hu, J. Du, P. Chen, H. M. Nguyen, P. Quinlan and R. B. Staszewski, “A type-II phase-tracking receiver”, IEEE Journal of Solid-State Circuits (JSSC), vol. 56, iss. 2, pp. 427–439, Feb. 2021. DOI: 10.1109/JSSC.2020.3005797. [IEEE Xplore link (Open Access)]
[29] A. Bozorg and R. B. Staszewski, “A 20 MHz–2 GHz inductorless two-fold noise-canceling low-noise amplifier in 28-nm CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 69, iss. 1, pp. 42–50, Jan. 2021. DOI: 10.1109/TCSI.2021.3092960. [IEEE Xplore link (Open Access)]
[30] G. Nikandish, R. B. Staszewski and A. Zhu, “A fully integrated GaN dual-channel power amplifier with crosstalk suppression for 5G massive MIMO transmitters”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 1, iss. 68, pp. 246–250, Jan. 2021. DOI: 10.1109/TCSII.2020.3008365. [IEEE Xplore link]
2020
[1] G. Nikandish, R. B. Staszewski and A. Zhu, “A fully integrated GaN dual-channel power amplifier with crosstalk suppression for 5G massive MIMO transmitters”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 1, iss. 68, pp. 246–250, Jan. 2020. DOI: 10.1109/TCSII.2020.3008365. [IEEE Xplore link]
[2] G. Nikandish, R. B. Staszewski and A. Zhu, “Broadband Fully Integrated GaN Power Amplifier With Minimum-Inductance BPF Matching and Two-Transistor AM-PM Compensation”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 67, iss. 12, pp. 4211–4223, Dec. 2020. DOI: 10.1109/TCSI.2020.3002395. [IEEE Xplore link]
[3] C.-C. Li, M.-S. Yuan, Y.-T. Lin, C.-C. Liao, C.-H. Chang and R. B. Staszewski, “A 0.2-V three-winding transformer-based DCO in 16-nm FinFET CMOS”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 67, iss. 12, pp. 2878-2882, Dec. 2020. DOI: 10.1109/TCSII.2020.2989415. [IEEE Xplore link (Open Access)]
[4] H. Wang, V. Nguyen, F. Schembari and R. B. Staszewski, “An adaptive-resolution quasi-level-crossing Delta modulator with VCO-based residue quantizer”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 67, iss. 12, pp. 2828–2832, Dec. 2020. DOI: 10.1109/TCSII.2020.2979078. [IEEE Xplore link (Open Access)]
[5] A. Urso, Y. Chen, R. B. Staszewski, J. Dijkhuis, S. Stanzione, Y.-H. Liu, W. Serdijn and M. Babaie, “A Switched-Capacitor DC-DC Converter Powering an LC Oscillator to Achieve 85% System Peak Power Efficiency and -65dBc Spurious Tones”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 67, iss. 11, pp. 3764-3777, Nov. 2020. DOI: 10.1109/TCSI.2020.3012106. [IEEE Xplore link (Open Access)]
[6] M. Bagheri, F. Schembari, N. Pourmousavian, H. Zare-Hoseini, D. Hasko and R. B. Staszewski, “A mismatch calibration technique for SAR ADCs based on deterministic self-calibration and stochastic quantization”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 67, iss. 9, pp. 2883–2896, Sept. 2020. DOI: 10.1109/TCSI.2020.2985816. [IEEE Xplore link (Open Access)]
[7] A. Esmailiyan, H. Wang, M. Asker, E. Koskin, D. Leipold, I. Bashir, K. Xu, A. Koziol, E. Blokhina and R. B. Staszewski, “A Fully Integrated DAC for CMOS Position-Based Charge Qubits with Single-Electron Detector Loopback Testing”, IEEE Solid-State Circuits Letters (SSC-L), vol. 3, pp. 354–357, 24 Aug. 2020. DOI:10.1109/LSSC.2020.3018707. [IEEE Xplore link (Open Access)]
[8] Y. Wu, P. Lu and R. B. Staszewski, “A time-domain 147 frms 2.5 MHz bandwidth two-step flash-MASH 1-1-1 time-to-digital converter with 3rd-order noise-shaping and mismatch correction”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 67, iss. 8, pp. 2532–2545, Aug. 2020. DOI: 10.1109/TCSI.2020.2983581. [IEEE Xplore link (Open Access)]
[9] K. Xu, J. Yin, P.-I. Mak, R. B. Staszewski and R. P. Martins, “A single-pin antenna interface RF front-end using a single-MOS DCO-PA and a push-pull LNA”, IEEE Journal of Solid-State Circuits (JSSC), vol. 55, iss. 8, pp. 2055–2068, Aug. 2020. DOI: 10.1109/JSSC.2020.2991520. [IEEE Xplore link (Open Access)]
[10] G. Nikandish, R. B. Staszewski and A. Zhu, “A fully integrated reconfigurable multi-mode class-F2,3 GaN power amplifier”, IEEE Solid-State Circuits Letters (SSC-L), vol. 3, pp. 270–273, 31 Jul. 2020. DOI: 10.1109/LSSC.2020.3013430. [IEEE Xplore link]
[11] I. Bashir, E. Blokhina, A. Esmailiyan, D. Leipold, M. Asker, E. Koskin, P. Giounanlis, H. Wang, D. Andrade-Miceli, A. Sokolov,A. Koziol, T. Siriburanon and R. B. Staszewski, “A Single-Electron Injection Device for CMOS Charge Qubits Implemented in 22 nm FD-SOI”, IEEE Solid-State Circuits Letters (SSC-L), vol. 3, pp. 206–209, 21 Jul. 2020. DOI: 10.1109/LSSC.2020.3010822. [IEEE Xplore link (Open Access)]
[12] T.-H. Tsai, R.-B. Sheen, C.-H. Chang, K. C.-H. Hsieh and R. B. Staszewski, “A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment with 0.6 us Settling, 0.619 ps Integrated Jitter and -240.5 dB FoM in 7-nm FinFET”, IEEE Solid-State Circuits Letters (SSC-L), vol. 3, iss. x, pp. 174–177, 20 Jul. 2020. DOI: 10.1109/LSSC.2020.3010278. [IEEE Xplore link (Open Access)]
[13] X. Chen, Y. Hu, T. Siriburanon, J. Du, R. B. Staszewski and A. Zhu, “A Tiny Complementary Oscillator with 1/f3 Noise Reduction Using a Triple-8-Shaped Transformer”, IEEE Solid-State Circuits Letters (SSC-L), vol. 3, pp. 162–165, 14 Jul. 2020. DOI: 10.1109/LSSC.2020.3009205. [IEEE Xplore link (Open Access)]
[14] J. Du, T. Siriburanon, Y. Hu, V. Govindaraj and R. B. Staszewski, “A 2.0–2.87GHz -249dB FoM 1.1 mW Digital PLL Ex- ploiting Reference-Sampling Phase Detector”, IEEE Solid-State Circuits Letters (SSC-L), vol. 3, pp. 158–161, 9 Jul. 2020. DOI: 10.1109/LSSC.2020.3008298. [IEEE Xplore link]
[15] A. Esmailiyan, F. Schembari and R. B. Staszewski, “A 0.36-V 5-MS/s time-mode flash ADC with Dickson-charge-pump-based comparators in 28-nm CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 67, iss. 6, pp. 1789–1802, Jun. 2020. DOI: 10.1109/TCSI.2020.2969804. [IEEE Xplore link (Open Access)]
[16] G. Nikandish, R. B. Staszewski and A. Zhu, “Breaking bandwidth limit: A review of broadband Doherty power amplifier design for 5G”, IEEE Microwave Magazine, vol. 21, no. 4, pp. 57–75, Apr 2020. DOI: 10.1109/MMM.2019.2963607. [IEEEXplore link]
[17] H. Wang, F. Schembari and R. B. Staszewski, “An event-driven quasi-level-crossing delta modulator based on residue quantization”, IEEE Journal of Solid-State Circuits (JSSC), vol. 55, iss. 2, pp. 298–311, Feb. 2020. DOI: 10.1109/JSSC.2019.2950175. [IEEE Xplore link (Open Access)]
[18] H. Wang, F. Schembari and R. B. Staszewski, “Passive SC ΔΣ modulator based on pipelined charge-sharing rotation in 28-nm CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 67, iss. 2, pp. 578–589, Feb. 2020. DOI: 10.1109/TCSI.2019.2944467. [IEEE Xplore link (Open Access)]
[19] K.-F. Un, F. Zhang, P.-I. Mak, R. P. Martins, A. Zhu and R. B. Staszewski, “Design considerations of the interpolative digital transmitter for quantization noise and replicas rejection”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 67, iss. 1 pp. 37–41, Jan. 2020. DOI: 10.1109/TCSII.2019.2903561. [IEEE Xplore link]
2019
[1] E. Blokhina, P. Giounanlis, A. Mitchell, D. Leipold and R. B. Staszewski, “CMOS position-based charge qubits: theoretical analysis of control and entanglement”, IEEE Access, vol. 8, pp. 4182–4197, Dec. 2019. DOI: 10.1109/ACCESS.2019.2960684. [IEEE Xplore link (Open Access)]
[2] Y. Hu, T. Siriburanon and R. B. Staszewski, “Intuitive understanding of flicker noise reduction via narrowing of conduction angle in voltage-biased oscillators”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 66, iss. 12 pp. 1962–1966, Dec. 2019. DOI: 10.1109/TCSII.2019.2896483. [IEEE Xplore link (Open Access)]
[3] K. Pomorski, P. Giounanlis, E. Blokhina, D. Leipold and R. B. Staszewski, “Analytic view on coupled single-electron lines”, IOP Science – Semiconductor Science and Technology, vol. 34, no. 12, pp. 1–12, 20 Nov. 2019.(125015) DOI: 10.1088/1361-6641/ab4f40. [IOP link (journal link)] [IOP link (Open Access)]
[4] P. Chen, F. Zhang, Z. Zong, S. Hu, T. Siriburanon and R. B. Staszewski, “A 31-µW, 148-fs step, 9-bit capacitor-DAC-based constant-slope digital-to-time converter in 28-nm CMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 54, iss. 11, pp.3075–3085, Nov. 2019. DOI: 10.1109/JSSC.2019.2939663. [IEEE Xplore link (Open Access)]
[5] P. Giounanlis, E. Blokhina, D. Leipold and R. B. Staszewski, “Photon enhanced interaction and entanglement in semiconductor position-based qubits”, MDPI Applied Sciences, Special Issue in Optics for AI and AI for Optics, pp. 1–15, 25 Oct. 2019. DOI:10.3390/app9214534. [MDPI Special Issue link] [MDPI link (Open Access)]
[6] G. Nikandish, R. B. Staszewski and A. Zhu, “Broadband fully integrated GaN power amplifier with embedded minimum inductor bandpass filter and AM-PM compensation”, IEEE Solid-State Circuits Letters (SSC-L), vol. 2, iss. 9, pp. 159–162, Sept. 2019. DOI: 10.1109/LSSC.2019.2927855. [IEEE Xplore link]
[7] G. Shehata, M. Keaveney and R. B. Staszewski, “A 184.6-dBc/Hz FOM 100-kHz flicker phase noise corner 30-GHz rotary traveling-wave oscillator using distributed stubs in 22-nm FD-SOI”, IEEE Solid-State Circuits Letters (SSC-L), vol. 2, iss. 9, pp. 103–106, Sept. 2019. DOI: 10.1109/LSSC.2019.2929326. [IEEE Xplore link]
[8] G. Nikandish, R. B. Staszewski and A. Zhu, “Bandwidth enhancement of GaN MMIC Doherty power amplifiers using broadband transformer-based load modulation network”, IEEE Access, vol. 07, pp. 119844–119855, Aug. 2019. DOI: 10.1109/ACCESS.2019.2937388. [IEEE Xplore link (Open Access)]
[9] M. Salarpour, F. Farzaneh and R. B. Staszewski, “Synchronization-phase alignment of all-digital phase-locked loop chips for a 60-GHz MIMO transmitter and evaluation of phase noise effects”, IEEE Trans. on Microwave Theory and Techniques (TMTT), vol. 67, no. 7, pp. 3187–3199, Jul. 2019. DOI: 10.1109/TMTT.2019.2910060. [IEEE Xplore link (Open Access)]
[10] U. Kamath, E. Cullen, T. Yu, J. Jennings, S. Wu, P. Lim, B. Farley and R. B. Staszewski, “A 1-V bandgap reference in 7-nm FinFET with a programmable temperature coefficient and inaccuracy of ±0.2% from -45℃ to 125℃” , IEEE Journal of Solid-State Circuits (JSSC), vol. 54, iss. 7, pp. 1830–1840, Jul. 2019. DOI: 10.1109/JSSC.2019.2919134. [IEEE Xplore link]
[11] K. Xu, F.-W. Kuo, R. Chen, L.-C. Cho, C.-P. Jou, M. Chen and R. B. Staszewski, “A 0.85 mm2 51%-efficient 11 dB compact DCO-DPA in 16-nm FinFET for sub-GHz IoT TX using HD2 self-suppression and pulling mitigation”, IEEE Journal of Solid-State Circuits (JSSC), vol. 54, iss. 7, pp. 2028–2037, Jul. 2019. DOI: 10.1109/JSSC.2019.2906803. [IEEE Xplore link (Open Access)]
[12] G. Nikandish, R. B. Staszewski and A. Zhu, “Design of highly linear broadband continuous mode GaN MMIC power amplifiers for 5G” , IEEE Access, vol. 7, pp. 57138–57150, May. 2019. DOI: 10.1109/ACCESS.2019.2914563. [IEEE Xplore link (Open Access)]
[13] P. Giounanlis, E. Blokhina, K. Pomorski, D. Leipold and R. B. Staszewski, “Modeling of semiconductor electrostatic qubits realized through coupled quantum dots”, IEEE Access, vol. 7, pp. 49262–49278, April. 2019. DOI: 10.1109/ACCESS.2019.2909489. [IEEE Xplore link (Open Access)]
[14] M. Keshavarz Hedayati, A. Abdipour, R. Sarraf, M. J. Ammann, M. John, C. Cetintepe and R. B. Staszewski, “Challenges in on-chip antenna design and integration with RF receiver front-end circuitry in nanoscale CMOS for 5G communication systems” , IEEE Access, vol. 7, iss. 1, pp. 43190–43204, Apr. 2019. DOI: 10.1109/ACCESS.2019.2905861. [IEEE Xplore link (Open Access)]
[15] Y.-H. Liu, V. K. Purushothaman, C. Bachman and R. B. Staszewski, “Design and analysis of a DCO-based phase-tracking RF receiver for IoT applications”, IEEE Journal of Solid-State Circuits (JSSC), vol. 54, iss. 3, pp. 785–795, Mar 2019. DOI:10.1109/JSSC.2018.2883398. [IEEE Xplore link]
[16] Z. Zong, P. Chen and R. B. Staszewski, “A low-noise fractional-N digital frequency synthesizer with Implicit frequency tripling for mm-wave applications”, IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 3, pp. 755–767, Mar. 2019. DOI:10.1109/JSSC.2018.2883397. [IEEE Xplore link (Open Access)]
[17] Y. Chen, Y.-H. Liu, Z. Zong, J. Dijkhuis, G. Dolmans, R. B. Staszewski and M. Babaie, “A supply pushing reduction technique for LC oscillators based on ripple replication and cancellation”, IEEE Journal of Solid-State Circuits (JSSC), vol. 54, iss. 1, pp. 240–252, Jan. 2019. DOI: 10.1109/JSSC.2018.2871195. [IEEE Xplore link (Open Access)]
2018
[1] C.-C. Li, M.-S. Yuan, C.-C. Liao, Y.-T. Lin, C.-H. Chang and R. B. Staszewski, “All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply”, IEEE Journal of Solid-State Circuits (JSSC), vol. 53, iss. 12, pp. 3660–3671, Dec. 2018. DOI: 10.1109/JSSC.2018.2871632. [IEEE Xplore link]
[2] V. Nguyen, F. Schembari and R. B. Staszewski, “A 0.2-V 30-MS/s 11b-ENOB open-loop VCO-based ADC in 28-nm CMOS”, IEEE Solid-State Circuits Letters (SSC-L), vol. 1, iss. 9, pp. 190–193, Sept. 2018. DOI: 10.1109/LSSC.2019.2906777. [IEEE Xplore link (Open Access)]
[3] P. Chen, X. Huang, Y. Chen, L. Wu and R. B. Staszewski, “An on-chip self-characterization of a digital-to-time converter by embedding it in a first-order ΔΣ loop”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 65, iss. 11, pp. 3734–3744, Nov. 2018. DOI: 10.1109/TCSI.2018.2857999. [IEEE Xplore link (Open Access)]
[4] F.-W. Kuo, M. Babaie, H.-N. R. Chen, L.-C. Cho, C.-P. Jou, M. Chen and R. B. Staszewski, “An all-digital PLL for cellular mobile phones in 28 nm CMOS with -55 dBc fractional and -91 dBc reference spurs”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 65, iss. 11, pp. 3756–3768, Nov. 2018. DOI: 10.1109/TCSI.2018.2855972. [IEEE Xplore link (Open Access)]
[5] M. Keshavarz Hedayati, A. Abdipour, R. Sarraf Shirazi, C. Cetintepe and R. B. Staszewski, “A 33-GHz LNA for 5G wireless systems in 28-nm bulk CMOS”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. xx, iss. 10, pp. 1460–1464, Oct. 2018. DOI: 10.1109/TCSII.2018.2859187. [IEEE Xplore link (Open Access)]
[6] N. Pourmousavian, F.-W. Kuo, T. Siriburanon, M. Babaie and R. B. Staszewski, “A 0.5-V 1.6-mW 2.4-GHz fractional-N alldigital PLL for Bluetooth LE with PVT-Insensitive TDC using switched-capacitor doubler in 28-nm CMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 53, no. 9, pp. 2572–2583, Sept. 2018. DOI: 10.1109/JSSC.2018.2843337. [IEEE Xplore link (Open Access)]
[7] H.Wang, F. Schembari, M. Miskowicz and R. B. Staszewski, “An adaptive-resolution quasi-level-crossing-sampling ADC based on residue quantization in 28-nm CMOS”, IEEE Solid-State Circuits Letters (SSC-L), vol. 1, iss. 8, pp. 178–181, Aug. 2018. DOI:10.1109/LSSC.2019.2899723. [IEEE Xplore link (Open Access)]
[8] Y.-T. Lin, N. Pourmousavian, C.-C. Li, M.-S. Yuan, C.-H. Chang and R. B. Staszewski, “A 180 mV 81.2%-efficient switched–capacitor voltage doubler for IoT using self-biasing deep N-Well in 16-nm CMOS FinFET”, IEEE Solid-State Circuits Letters (SSC-L), vol. 1, iss. 7, pp. 158–161, July 2018. DOI: 10.1109/LSSC.2018.2889422. [IEEE Xplore link (Open Access)]
[9] M. Salarpour, F. Farzaneh and R. B. Staszewski, “A low cost–low loss broadband integration of a CMOS transmitter and its antenna for mm-Wave FMCW radar applications”, Elsevier, AEU - International Journal of Electronics and Communications, vol. 95, pp. 313–325, Aug. 2018 (first online 25 Aug. 2018). DOI: 10.1016/j.aeue.2018.08.032. [Elsevier link]
[10] M. Salarpour, F. Farzaneh and R. B. Staszewski, “Design and calibration procedure of a proposed V-band antenna array on fused silica technology intended for MIMO applications”, International Journal of Microwave and Optical Technology (IJMOT), vol. 13, no. 4, pp. 317–329, July 2018.
[11] Y. Hu, T. Siriburanon and R. B. Staszewski, “A low-flicker-noise 30-GHz class-F23 oscillator in 28-nm CMOS using implicit resonance and explicit common-mode return path”, IEEE Journal of Solid-State Circuits (JSSC), vol. 53, no. 7, pp. 1977–1987, July. 2018. DOI: 10.1109/JSSC.2018.2818681. [IEEE Xplore link (Open Access)]
[12] G. Nikandish, R. B. Staszewski and A. Zhu, “The (R)evolution of Distributed Amplifiers: From Vacuum Tubes to Modern CMOS and GaN ICs ”, IEEE Microwave Magazine, vol. 19, no. 4, pp. 66–83, June. 2018. DOI: 10.1109/MMM.2018.2813838. [IEEE Xplore link]
[13] R. Lotfi, M. Saberi, S. R. Hosseini, A. R. Ahmadi-Mehr and R. B. Staszewski, “Energy-efficient wide-range voltage level shifters reaching 4.2 fJ/transition”, IEEE Solid-State Circuits Letters (SSCL), vol. 1, iss. 2, pp. 34–37, Feb. 2018. DOI: 10.1109/LSSC.2018.2810606. [IEEE Xplore link]
[14] B. Patra, R. M. Incandela, J. P.G. van Dijk, H. A.R. Homulle, L. Song, M. Shahmohammadi, R. B. Staszewski, A. Vladimirescu, M. Babaie, F. Sebastiano, and E. Charbon, “Cryo-CMOS circuits and systems for quantum computing applications”, IEEE Journal of Solid-State Circuits (JSSC), vol. 53, no. 1, pp. 309–321, Jan. 2018. DOI: 10.1109/JSSC.2017.2737549. [IEEE Xplore link (Open Access)]
2017
[1] A. R. Ximenes, G. Vlachogiannakis and R. B. Staszewski, “An ultra-compact 9.4–14.8 GHz transformer-based fractional-N all-digital PLL in 40 nm CMOS”, IEEE Trans. on Microwave Theory and Techniques (TMTT), vol. 65, no. 11, pp.4241–4254, 4254, 2017. DOI: 10.1109/TMTT.2017.2687901. [IEEE Xplore link (Open Access)]
[2] Y. Wu, M. Shahmohammadi, Y. Chen, P. Lu and R. B. Staszewski, “A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise”, IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 7, pp. 1885–1903, Jul. 2017. DOI: 10.1109/JSSC.2017.2682841. [IEEE Xplore link (Open Access)]
[3] I. Bashir, R. B. Staszewski and P. Balsara, “Numerical model of an injection-locked wideband frequency modulator for polar transmitters”, IEEE Trans. on Microwave Theory and Techniques (TMTT), vol. 65, no. 5, pp. 1914–71920, May. 2017. DOI: 10.1109/TMTT.2016.2634537. [IEEE Xplore link (Open Access)]
[4] S. Binsfeld Ferreira, F.-W. Kuo, M. Babaie, B. Sergio and R. B. Staszewski, “System design of a 2.75mW discrete time superheterodyne receiver for Bluetooth low energy”, IEEE Trans. on Microwave Theory and Techniques (TMTT), vol. 65, no. 5, pp. 1904–1913, May. 2017. DOI: 10.1109/TMTT.2017.2668407. [IEEE Xplore link (Open Access)]
[5] Y.-H. Liu, J. vd Heuvel, T. Kuramochi, B. Busze, P. Mateman, V. K. Chillara, B.Wang, R. B. Staszewski and K. Philips, “An ultra-low power 1.7-2.7 GHz fractional-N sub-sampling digital frequency synthesizer and modulator for IoT applications in 40 nm CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 64, iss. 5, pp. 1094–1105, May. 2017. DOI: 10.1109/TCSI.2016.2625462. [IEEE Xplore link]
[6] M. Shahmohammadi, M. Babaie and R. B. Staszewski, “Tuning Range Extension of a Transformer-Based Oscillator through Common-Mode Colpitts Resonance”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 64, iss. 4, pp. 836–846, Apr. 2017. DOI: 10.1109/TCSI.2016.2625199. [IEEE Xplore link (Open Access)]
[7] F.-W. Kuo, S. Binsfeld Ferreira, H.-N. R. Chen, L.-C. Cho, C.-P. Jou, F.-L. Hsueh, I. Madadi, M. Tohidian, M. Shahmohammadi, M. Babaie and R. B. Staszewski, “A Bluetooth low-energy transceiver with 3.7-mW all-digital transmitter, 2.75-mW high-IF discrete-time receiver, and TX/RX switchable on-chip matching network”, IEEE Journal of Solid- State Circuits (JSSC), vol. 52, iss. 4, pp. 1144–1162, Apr. 2017. DOI: 10.1109/JSSC.2017.2654322. [IEEE Xplore link (Open Access)]
[8] M. Tohidian, I. Madadi and R. B. Staszewski, “A fully integrated discrete-time superheterodyne receiver”, IEEE Trans. on VLSI Systems (TVLSI), vol. 25, no. 2, pp. 635–647, Feb. 2017. DOI: 10.1109/TVLSI.2016.2598857. [IEEE Xplore link (Open Access)]
2016
[1] M. Shahmohammadi, M. Babaie and R. B. Staszewski, “A 1/f noise upconversion reduction technique for voltagebiased RF CMOS oscillators”, IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 11, pp. 2610–2624, Nov. 2016. DOI: 10.1109/JSSC.2016.2602214. [IEEE Xplore link (Open Access)]
[2] I. Bashir, R. B. Staszewski, O. E. Eliezer and P. T. Balsara, “A wideband digital-to-frequency converter with built-In mechanism for self-interference mitigation”, Journal of Electronic Testing (JETTA): Theory and Applications; Special Issue on Analog, Mixed-Signal and RF Testing, vol. 32, no. 4, pp. 437–445, Aug. 2016 (first online 14 Jul. 2016). DOI: 10.1007/s10836-016-5607-z.[Splinger link] [Splinger read-only link]
[3] M. Babaie, F.-W. Kuo, R. Chen, L.-C. Cho, C.-P. Jou, F.-L. Hsueh, M. Shahmohammadi and R. B. Staszewski, “A Fully Integrated Bluetooth Low-Energy Transmitter in 28-nm CMOS with 36% System Efficiency at 3 dBm”, IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 7, pp. 1547–1565, Jul. 2016. DOI: 10.1109/JSSC.2016.2551738. [IEEE Xplore link (Open Access)]
[4] I. Bashir, R. B. Staszewski and P. T. Balsara, “A digitally controlled injection locked oscillator with fine frequency resolution”, IEEE Journal of Solid-State Circuits (JSSC), vol. 51, iss. 6, pp. 1347–1360, June 2016. DOI: 10.1109/JSSC.2016.2539342. [IEEEXplore link (Open Access)]
[5] Z. Zong, M. Babaie and R. B. Staszewski, “A 60 GHz frequency generator based on a 20 GHz oscillator and an implicit multiplier”, IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 5, pp. 1261–1273, May 2016. DOI: 10.1109/JSSC.2016.2528997. [IEEE Xplore link (Open Access)]
[6] S. A.-R. Ahmadi-Mehr, M. Tohidian and R. B. Staszewski, “Analysis and design of a multi-core oscillator for ultra-low phase noise”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 63, iss. 4, pp. 529–539, Apr. 2016. DOI: 10.1109/TCSI.2016.2529218. [IEEE Xplore link (Open Access)]
[7] S. A. R. Ahmadi Mehr, M. Tohidian and R. B. Staszewski, “Toward solving multichannel RF-SoC integration issues through digital fractional division”, IEEE Trans. on VLSI Systems (TVLSI), vol. 24, no. 3, pp. 1071–1082, Mar. 2016. DOI: 10.1109/TVLSI.2015.2436979. [[IEEE Xplore link (Open Access)]
[8] I. Madadi, M. Tohidian, K. Cornelissens, P. Vandenameele and R. B. Staszewski, “A high IIP2 SAW-less superhetero-dyne receiver with multi-stage harmonic rejection”, IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 2, pp. 332–347, Feb. 2016. DOI: 10.1109/JSSC.2015.2504414. [IEEE Xplore link (Open Access)]
2015
[1] I. Madadi, M. Tohidian and R. B. Staszewski, “Analysis and design of I/Q charge-sharing band-pass-filter for superheterodyne receivers”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 62, iss. 8, pp. 2114–2121, Aug. 2015. DOI: 10.1109/TCSI.2015.2437514. [IEEE Xplore link (Open Access)]
[2] M. Tohidian, A.-R. Ahmadi-Mehr and R. B. Staszewski, “A tiny quadrature oscillator using low-Q series LC tanks”, IEEE Microwave and Wireless Components Letters (MWCL), vol. 25, no. 8, pp. 520,–522, Aus. 2015. DOI: 10.1109/LMWC.2015.2440663. [IEEE Xplore link (Open Access)]
[3] G. Hueber, J. Tsutsumi, M. Seth, A. S. Morris and R. B. Staszewski, “Cost-efficient, high-volume transmission”, IEEE Microwave Magazine, vol. 16, no. 7, pp. 26–45, Aug. 2015. DOI: 10.1109/MMM.2015.2431235. [IEEE Xplore link]
[4] M. Babaie and R. B. Staszewski, “An ultra-low phase noise class-F2 CMOS oscillator with 191 dBc/Hz FoM long-term reliability”, IEEE Journal of Solid-State Circuits (JSSC), vol. 50, no. 3, pp. 679–692, Mar. 2015. DOI: 10.1109/JSSC.2014.2379265. [IEEE Xplore link (Open Access)]
[5] J. Zhuang, K. Waheed and R. B. Staszewski, “Design of spur-free sigma-delta frequency tuning interface for digitally controlled oscillators”, IEEE Trans. on Circuits and Systems II (TCAS-II),vol. 62, iss. 1, pp. 46–50, Jan. 2015. DOI: 10.1109/TC-SII.2014.2362692. [IEEE Xplore link]
2014
[1] M. Tohidian, I. Madadi and R. B. Staszewski, “Analysis and design of a high-order discrete-time passive IIR low-pass filter”, IEEE Journal of Solid-State Circuits(JSSC), vol. 49, iss. 11, pp. 2575–2587, Nov. 2014. DOI: 10.1109/JSSC.2014.2359656. [IEEE Xplore link (Open Access)]
[2] K. Kang, Z. Zong, Z. Gao, Y.-L. Ban, B. Staszewski and W.-Y. Yin, “Characterization and modeling of multiple coupled inductors based on on-chip four-port measurement”, IEEE Trans. on Components, Packaging and Manufacturing Technology (TCPMT), vol. 4, no. 10, pp. 1696–1704, Oct. 2014. DOI: 10.1109/TCPMT.2014.2347965. [IEEE Xplore link]
[3] X. Luo, S. Sun and R. B. Staszewski, “Tunable bandpass filter with two adjustable transmission poles and compensable coupling”, IEEE Trans. on Microwave Theory and Techniques (TMTT), vol.62, no.9, pp.2003–2013, Sept. 2014. DOI: 10.1109/TMTT.2014.2337287. [IEEE Xplore link (Open Access)]
[4] W. Wu, R. B. Staszewski and J. R. Long, “A 56.4-to-63.4 GHz multi-rate all-digital fractional-N PLL for FMCW radar applications in 65-nm CMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 49, iss. 5, pp. 1081–1096, May. 2014. DOI: 10.1109/JSSC.2014.2301764. [IEEE Xplore link (Open Access)]
[5] M. S. Alavi, R. B. Staszewski, L. C. N. de Vreede and J. R. Long, “A wideband 2x13-bit all-digital I/Q RF-DAC”, IEEE Trans. on Microwave Theory and Techniques (TMTT), vol. 62, no. 4, pp. 732–752, Apr. 2014. DOI: 10.1109/TMTT.2014.2307876. [IEEE Xplore link (Open Access)]
[6] J. Zhuang and R. B. Staszewski, “All-digital RF phase-locked loops exploiting phase prediction” (Invited), Information Processing Society of Japan (IPSJ) Transactions on System LSI Design Methodology (T-SLDM), https://www.jstage.jst.go.jp/browse/ipsjtsldm, vol. 7, pp. 2–15, Feb. 2014. DOI: 10.2197/ipsjtsldm.7.2. [IPSJ link (Open Access)]
[7] A. Visweswaran, R. B. Staszewski and J. R. Long, “A low phase noise oscillator principled on transformer-coupled hard limiting”, IEEE Journal of Solid-State Circuits (JSSC), vol. 49, iss. 2, pp. 373–383, Feb. 2014. DOI: 10.1109/JSSC.2013.2285375. [IEEE Xplore link]
2013
[1] M. Babaie and R. B. Staszewski, “A class-F CMOS oscillator”, IEEE Journal of Solid-State Circuits(JSSC),vol. 48, iss. 12, pp. 3120–3133, Dec. 2013. DOI: 10.1109/JSSC.2013.2273823. [IEEE Xplore link (Open Access)]
[2] W. Wu, J. R. Long and R. B. Staszewski, “High-resolution millimeter-wave digitally controlled oscillators with reconfigurable passive resonators”, IEEE Journal of Solid-State Circuits(JSSC),vol. 48, iss. 11, pp. 2785–2794, Nov. 2013. DOI: 10.1109/JSSC.2013.2282701. [IEEE Xplore link]
2012
[1] R. B. Staszewski,“Digitally intensive wireless transceivers”(Invited), IEEE Design and Test of Computers, vol. 29, iss. 6, pp. 7–18, Nov/Dec. 2012. DOI: 10.1109/MDT.2012.2209392. [IEEE Xplore link]
[2] M. S. Alavi, R. B. Staszewski, L. C. N. de Vreede, A. Visweswaran and J. R. Long, “All digital RF I/Q modulator”, IEEE Trans. on Microwave Theory and Techniques (TMTT), vol. 60, no. 11, pp. 3513–3526, Nov. 2012. DOI: 10.1109/TMTT.2012.2211612. [IEEE Xplore link]
2011
[1] R. B. Staszewski, K. Waheed, F. Dulger, and O. Eliezer, “Spur-free multirate all-digital PLL for mobile phones in 65nm CMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 46, iss. 12, pp. 2904–2919, Dec. 2011. DOI: 10.1109/JSSC.2011.2162769. [IEEE Xplore link]
[2] M. Park, M. H. Perrott and R. B. Staszewski, “An amplitude resolution improvement of an RF-DAC employing pulsewidth modulation”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 58, iss. 11, pp. 2590–2603, Nov. 2011. DOI: 10.1109/TCSI.2011.2143030. [IEEE Xplore link]
[3] K.Waheed, R. B. Staszewski, F. Dulger, M. S. Ullah and S. D. Vamvakos, “Spurious-free time-to-digital conversion in an ADPLL using short dithering sequences”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 58, iss. 9, pp. 2051–2060, Sept. 2011. DOI: 10.1109/TCSI.2011.2163981. [IEEE Xplore link]
[4] R. B. Staszewski, “State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 58, iss. 7, pp. 1497–1510, July 2011. DOI: 10.1109/TCSI.2011.2150890. [IEEE Xplore link]
[5] O. Eliezer and R. B. Staszewski, “Built-in measurements in low-cost digital-RF transceivers” (Invited), IEICE Trans. Electronics; Special Session on Analog Circuits and Related SoC Integration Technologies, vol. E94-C, no. 6, pp. 930–937, April 2011. DOI: 10.1109/TCSI.2011.2150890. [IEICE link (Open Access)]
[6] I. Bashir, R. B. Staszewski, O. Eliezer, B. Banerjee and P. T. Balsara, “A novel approach for mitigation of RF oscillator pulling in a polar transmitter”, IEEE Journal of Solid-State Circuits (JSSC), vol. 46, iss. 2, pp. 403–415, Feb. 2011. DOI: 10.1109/JSSC.2010.2096110. [IEEE Xplore link]
2010
[1] R. B. Staszewski, “Digital RF technology for expanding programmability of RF transceivers”, SK Telecom Journal - Reconfigurable RF Systems, vol. 20, no. 5, pp. 721–738, Oct. 2010.
[2] I. L. Syllaios, P. T. Balsara and R. B. Staszewski, “Recombination of envelope and phase paths in wideband polar transmitters”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 57, iss. 8, pp. 1891–1904, Aug. 2010. DOI: 10.1109/TCSI.2009.2039256. [IEEE Xplore link]
[3] J.-C. Zhuang, K. Waheed and R. B. Staszewski, “A technique to reduce phase/frequency modulation bandwidth in a polar RF transmitter”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 57, iss. 8, pp. 2196–2207, Aug. 2010. DOI: 10.1109/TCSI.2009.2037394. [IEEE Xplore link]
[4] M. Park, M. H. Perrott and R. B. Staszewski, “A time-domain resolution improvement of an RF-DAC”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 57, iss. 7, pp. 517–521, July 2010. DOI: 10.1109/TCSII.2010.2048485. [IEEE Xplore link]
[5] J. Mehta, V. Zoicas, O. Eliezer, R. B. Staszewski, S. Rezeq, M. Entezari and P. T. Balsara, “An efficient linearization scheme for a digital polar EDGE transmitter”, IEEE Trans. on Circuits and Systems II (TCAS-II),vol. 57, no. 3, pp. 193–197, Mar. 2010. DOI: 10.1109/TCSII.2010.2041811. [IEEE Xplore link]
[6] R. Staszewski, R. B. Staszewski, T. Jung, T. Murphy, I. Bashir, O. Eliezer, K. Muhammad and M. Entezari, “Software assisted Digital RF Processor (DRPTM) for single-chip GSM radio in 90 nm CMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 45, iss. 2, pp. 276–288, Feb. 2010. DOI: 10.1109/JSSC.2009.2036763. [IEEE Xplore link]
2009
[1] O. Eliezer, B. Staszewski, I. Bashir, S. Bhatara and P. T. Balsara, “A phase domain approach for mitigation of selfinterference in wireless transceivers”, IEEE Journal of Solid-State Circuits (JSSC),vol. 44, iss. 5, pp. 1436–1453, May. 2009. DOI: 10.1109/JSSC.2009.2014941. [IEEE Xplore link]
2008
[1] I. L. Syllaios, R. B. Staszewski and P. T. Balsara, “Time-domain modeling of an RF all-digital PLL”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 55, no. 6, pp. 601–604, Jun. 2008. DOI: 10.1109/TCSII.2007.916845. [IEEE Xplore link]
2007
[1] K. Muhammad, T. Murphy and R. B. Staszewski, “Verification of digital RF processors: RF, analog, baseband, and software”, IEEE Journal of Solid-State Circuits (JSSC), vol. 42, iss. 5, pp. 992–1002, May. 2007. DOI: 10.1109/JSSC.2007.894327. [IEEE Xplore link]
[2] R. B. Staszewski, I. Bashir and O. Eliezer, “RF built-in self test of a wireless transmitter”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 54, no. 2, pp. 186–190, Feb. 2007. DOI: 10.1109/TCSII.2006.886202. [IEEE Xplore link]
[3] R. B. Staszewski and P. T. Balsara, “All-digital PLL with ultra fast settling”, IEEE Trans. on Circuits and Systems II(TCAS-II),vol. 54, no. 2, pp. 181–185, Feb. 2007. DOI: 10.1109/TCSII.2006.886896. [IEEE Xplore link]
2006
[1] J. Koh, G. Gomez, K. Muhammad, R. B. Staszewski and B. Haroun, “A sigma-delta ADC with decimation and gain control function for a Bluetooth receiver in 130 nm digital CMOS”,EURASIP Journal on Wireless Communications and Networking, (available at http://jwcn.eurasipjournals.com/series/CMOS), vol. 2006, pp. Article ID 71249, 8 pages, 2006. DOI: 10.1155/WCN/2006/71249. [Eurasip link (Open Access)]
[2] Y.-C. Ho, R. B. Staszewski, K. Muhammad, C.-M. Hung, D. Leipold and K. Maggio, “Charge-domain signal processing of direct RF sampling mixer with discrete-time filters in Bluetooth and GSM receivers”, EURASIP Journal on Wireless Communications and Networking, (available at http://jwcn.eurasipjournals.com/series/CMOS), vol. 2006, pp. Article ID 62905, 14 pages, 2006. DOI: 10.1155/WCN/2006/62905. [Eurasip link (Open Access)]
[3] K. Muhammad, Y.-C. Ho, T. Mayhugh, C.-M. Hung, T. Jung, I. Elahi, C. Lin, I. Deng, C. Fernando, J. Wallberg, S. Vemulapalli, S. Larson, T. Murphy, D. Leipold, P. Cruise, J. Jaehnig, M.-C. Lee, R. B. Staszewski, R. Staszewski and K. Maggio, “The first fully integrated quad-band GSM/GPRS receiver in a 90-nm digital CMOS process”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, iss. 8, pp. 1772–1783, Aug. 2006. DOI: 10.1109/JSSC.2006.877271. [IEEE Xplore link]
[4] C.-M. Hung, R. B. Staszewski, N. Barton, M.-C. Lee and D. Leipold, “A digitally controlled oscillator system for SAW-less transmitters in cellular handsets”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, no. 5, pp. 1160–1170, May 2006. DOI: 10.1109/JSSC.2006.872739. [IEEE Xplore link]
[5] R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg and P. T. Balsara, “1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS”, IEEE Trans. on Circuits and Systems II (TCAS-II),vol. 53, no. 3, pp. 220–224, Mar. 2006. DOI: 10.1109/TCSII.2005.858754. [IEEE Xplore link]
[6] R. B. Staszewski, J. Wallberg, C.-M. Hung, G. Feygin, M. Entezari and D. Leipold, “LMS-based calibration of an RF digitally controlled oscillator for mobile phones”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 53, no. 3, pp. 225–229, Mar. 2006. DOI: 10.1109/TCSII.2005.858750. [IEEE Xplore link]
2005
[1] R. B. Staszewski, J.Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad and D. Leipold, “All-digital PLL and transmitter for mobile phones”, IEEE Journal of Solid-State Circuits (JSSC), vol. 40, iss. 12, pp. 2469–2482, Dec. 2005. DOI: 10.1109/JSSC.2005.857417. [IEEE Xplore link]
[2] R. B. Staszewski, R. Staszewski, J. L. Wallberg, T. Jung, C.-M. Hung, J. Koh, D. Leipold, K. Maggio and P. T. Balsara, “SoC with an integrated DSP and a 2.4-GHz RF transmitter”, IEEE Trans. on VLSI Systems (TVLSI), vol. 13, no. 11, pp. 1253–1265, Nov. 2005. DOI: 10.1109/TVLSI.2005.859587. [IEEE Xplore link]
[3] R. B. Staszewski, C.-M. Hung, N. Barton, M.-C. Lee and D. Leipold, “A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones”, IEEE Journal of Solid-State Circuits (JSSC), vol. 40, no. 11, pp. 2203–2211, Nov. 2005. DOI: 10.1109/JSSC.2005.857359. [IEEE Xplore link]
[4] K. Muhammad, R. B. Staszewski and D. Leipold, “Digital RF processing: toward low-cost reconfigurable radios”, IEEE Communications Magazine, vol. 43, no. 8, pp. 105–113, Aug. 2005. DOI: 10.1109/MCOM.2005.1497564. [IEEE Xplore link]
[5] R. B. Staszewski, D. Leipold and P. T. Balsara, “Direct frequency modulation of an ADPLL for Bluetooth/GSM with injection pulling elimination”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 52, no. 6, pp. 339–343, June 2005. DOI: 10.1109/TCSII.2005.848957. [IEEE Xplore link]
[6] R. B. Staszewski, C. Fernando and P. T. Balsara, “Event-driven simulation and modeling of phase noise of an RF oscillator”, IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 52, no. 4, pp. 723–733, Apr. 2005. DOI: 10.1109/TCSI.2005.844236. [IEEE Xplore link]
[7] R. B. Staszewski and P. T. Balsara, “Phase-domain all-digital phase-locked loop”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 52, no. 3, pp. 159–163, Mar. 2005. DOI: 10.1109/TCSII.2004.842067. [IEEE Xplore link]
2004
[1] R. B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J. L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I. Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. E. Eliezer, E. de-Obaldia and P. T. Balsara, “All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, iss. 12, pp. 2278–2291, Dec. 2004. DOI: 10.1109/JSSC.2004.836345. [IEEE Xplore link]
2003
[1] R. B. Staszewski, C.-M. Hung, D. Leipold and P. T. Balsara, “A first multigigahertz digitally controlled oscillator for wireless applications”, IEEE Trans. on Microwave Theory and Techniques (TMTT), vol. 51, no. 11, pp. 2154–2164, Nov. 2003. DOI: 10.1109/TMTT.2003.818579. [IEEE Xplore link]
[2] R. B. Staszewski, D. Leipold and P. T. Balsara, “Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 50, no. 11, pp. 887–892, Nov. 2003. DOI: 10.1109/TCSII.2003.819126. [IEEE Xplore link]
[3] R. B. Staszewski, D. Leipold, K Muhammad and P. T. Balsara, “Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 50, no. 11, pp. 815–828, Nov. 2003. DOI: 10.1109/TCSII.2003.819128. [IEEE Xplore link]
2001
[1] R. B. Staszewski, K. Muhammad and P. T. Balsara, “A constrained asymmetry LMS algorithm for PRML disk drive read channels”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 48, pp. 793–798, Aug. 2001. DOI: 10.1109/82.959872. [IEEE Xplore link]
[2] K. Muhammad, R. B. Staszewski and P. T. Balsara, “Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels”, IEEE Trans. on VLSI Systems (TVLSI), vol. 9, iss. 1, pp. 42–51, Feb. 2001. DOI: 10.1109/92.920818. [IEEE Xplore link]
2000
[1] R. B. Staszewski, K. Muhammad and P. Balsara, “A 550-MSample/s 8-tap FIR digital filter for magnetic recording read channels”, IEEE Journal of Solid-State Circuits (JSSC), vol. 35, iss. 8, pp. 1205–1210, Aug. 2000. DOI: 10.1109/4.859511. [IEEE Xplore link]
1997
[1] S. Kiriaki, T. L. Viswanathan, G. Feygin, B. Staszewski, R. Pierson, B. Krenik, M. de Wit and K. Nagaraj, “A 160- MHz analog equalizer for magnetic disk read channels”, IEEE Journal of Solid-State Circuits (JSSC), vol. 32, no. 11, pp. 1839–1850, Nov. 1997. DOI: 10.1109/4.641708. [IEEE Xplore link]