“An Event-Driven Quasi-Level-Crossing Delta Modulator Based on Residue Quantization”, IEEE Journal of Solid-State Circuits (JSSC), vol. 55, iss. 2, pp. 298–311, Feb. 2020.

Research lead: Hongying Wang. (Daily supervison by Dr. Filippo Schembari). We propose a digitally intensive event-driven quasi-level-crossing (quasi-LC) delta-modulator ADC with adaptive-resolution (AR) for IoT wireless networks. The proposed AR quasi-LC delta modulator quantizes the residue voltage signal with a 4-bit asynchronous SAR sub-ADC, which enables a straightforward implementation of LC and AR algorithms in digital domain. The proposed ADC achieves data compression by a globally signal-dependent sampling rate and achieves adaptive resolution through a digital multi-level comparison window which overcomes the trade-off between the dynamic range and input bandwidth in the conventional LC ADCs. The proposed ADC is fabricated in 28-nm CMOS and achieves an SNDR of 53 dB over a signal bandwidth of 1.42 MHz while consuming 205 µW and an active area of 0.0126 mm².

Research lead: Hongying Wang. (Daily supervison by Dr. Filippo Schembari).
We introduce a new switched-capacitor (SC) passive delta-sigma (ΔΣ) modulator architecture. It is based on a charge-sharing rotation technique, which eliminates any inter-stage loading effects that plague the conventional SC passive ΔΣ modulators. To improve the proposed modulator’s noise suppression and stability, an independent extra feedback path and a zeroing stage are added to the 2^nd –stage integrator. Moreover, a pipelining (i.e. interleaving) technique is employed in the passive low-pass filter to relax settling requirements and improve power efficiency. Compared to the ΔΣ modulators with active integrators, the proposed modulator contains only switches, capacitors and one comparator, thus being greatly amenable to nanoscale CMOS process nodes. Implemented in 28–nm CMOS, the proposed ADC occupies a core area of 0.059 mm² . It achieves measured SNDR of 81.1 dB and a measured dynamic range (DR) of 83.6 dB with a signal bandwidth of 80 kHz at 40.96 MS/s, while consuming 101.5 µW. SNDR is maintained above 70 dB across a ±20‰ supply variation.

Research lead: Viet Anh Nguyen. (Daily supervison by Dr. Filippo Schembari). We present A resistor-based frequency-tuning scheme helps in mitigating odd-order harmonic distortion induced by the VCO nonlinear transfer characteristic. It also provides a re-configurable input range, allowing it to exceed the supply by 2.5x (single-ended), and maintaining tolerance against ±10% supply variations. Latch, flip-flops and logic gate within the frequency-to-digital converter are designed for minimum propagation dealys, allowing sampling at 30MS/s. The ADC is implemented in 28-nm CMOS and achieves a peak SNDR of 68 dB, equivalent to an ENOB of 11, over a 61-kHz bandwith with a 1-V_pp input differential sinewave. It consumes 7 µW, resulting in a stage-of-the-art Walden and Schreier FoM of 27.8 fl/c-s and 167.4dB, respectively.

Research lead: Jianglin Du. (Daily supervison by Dr. Teerachot Siriburanon). We present a sub-mW ultra-low-voltage (ULV) digitally controlled oscillator (DCO) with vertically integrated switched capacitor banks under a transformer for area reduction. Exploiting a passive gain of the proposed transformer improves the DCO start-up. The reduced current conduction angle in this DCO has been proved to be an effective way in suppressing flicker noise upconversion while keeping wide tuning range (TR). Implemented in 28-nm CMOS, the proposed DCO achieves -95 dBc/Hz and -118dBc/Hz at 100 kHz and 1 MHz offsets, respectively. The TR is 35% from 2.02 GHz to 2.87 GHz. This results in a figure-of-merit with normalized TR (FoMT) at 100 kHz and 1 MHz offsets of -196 dB and -199 dB, respectively, which is a record among ‹0.6 V and ‹1 mW oscillators.

Research lead: Naser Pourmousavian. (Daily supervison by Dr. Teerachot Siriburanon). We propose an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry and regulates the TDC supply to stabilize its resolution thus maintaining fixed in-band phase noise (PN) across PVT. The ADPLL supports a 2-point modulation and forms a Bluetooth LE (BLE) transmitter realized in 28 nm CMOS. It achieves in-band PN of -106 dBc/Hz (FoM of -239.2 dB) and RMS jitter of 0.86 ps while dissipating only 1.6 mW at 40 MHz reference. The power consumption reduces to 0.8 mW during BLE transmission when the DCO switches to open-loop.

Research lead: Yizhe Hu. (Daily supervison by Dr. Teerachot Siriburanon). We present a mmW frequency generation stage aimed at minimizing phase noise via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A second-harmonic tank resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for shortest and well controlled common-mode current return path. Class-F operation with third harmonic boosting and extraction techniques allow maintaining high quality factor of a 10 GHz tank at the 30 GHz frequency generation while providing implicit divide-by-3 functionality. The proposed 27.3-31.2 GHz oscillator is implemented in 28-nm CMOS. It achieves phase noise of -106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of -184 dB at 27.3GHz. Its flicker phase noise corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW.

Research lead: Peng Chen. We propose a power-efficient capacitorarray-based digital-to-time converter (DTC) using a constantslope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 µW from a 1V supply, while achieving fine resolution of 103 fs when running at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves the best figure-of-merit of 8.5 fJ among stateof-the-art when normalizing the product of power and INL to the product of input frequency and range.

Research lead: Mahsa Keshavarz Hedayat. (Daily supervison by Dr. Cagri Cetintepe). We present a design procedure of a compact 33-GHz low-noise amplifier (LNA) for fifth generation (5G) applications realized in 28-nm LP CMOS. Based on the unique set of challenges presented by advanced nanoscale CMOS, the emphasis is put here on the optimization of design and layout techniques for active and passive components in the presence of rigorous metal density rules and other back-end-of-the-line challenges. All passive components are designed and optimized with full-wave electromagnetic simulations for a high quality factor. In addition, layout techniques help to miniaturize the total area as the suggested 5G frequency band of 33 GHz is not high enough to provide a sufficiently compact chip size. The resulting increase in the concentration of required metal fills furthermore makes this optimization more challenging. The fabricated LNA consists of two cascode stages with a total core area of 0.68×0.34 mm2. It exhibits 4.9-dB noise figure and 18.6-dB gain at 33 GHz while consuming only 9.7 mW from a 1.2-V power supply.

Research lead: Umanath Kamath. A 1-V precision voltage reference in 7-nm FinFET CMOS is presented. It allows to control a temperature coefficient of the generated voltage. Proposed trim techniques, favored for short test times, help to achieve good accuracy in spite of the challenges posed by the scaled technology and a ´hostile´ SoC environment. Two 2^nd-ordercurvature compensation techniques are implemented to achieve high accuracy. Measurement results show a max inaccuracy of ±0.2% with temperature coefficient as low as ∼6ppm/℃ over temperature range of 170℃(-45℃ to 125℃). Furthermore, the temperature coefficient is digitally programmable between -7 mV/100℃ to +8 mV/100℃, thus enabling temperature compensation for various sub-blocks within an FPGA. Line regulation is 0.1%/V. The whole design occupies 0.078 mm².

Research lead: Peng Chen. To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A system self-calibration algorithm is proposed to calibrate nonlinearities of the analog circuitry. The operation is robust over PVT variations since the delay information is normalized to the input clock period. To verify the proposed idea, two different digital-to-time converters performing the on-chip delay are measured and analyzed at 50-MHz clocking frequency with 0.65-ps standard time deviation per measurement.

Research lead: Kai Xu. We propose a power-efficient sub-lV RF front-end (RFE) for 2.4GHz transceivers. It introduces the following innovations: 1) function-reuse single-MOS VCO-PA with full FDd utilization while improving antenna-to-VCO isolation for better resilience to jammers; 2) a non-inverting transformer with a zero- shifting capacitor that suppresses the 2nd harmonic emission of the VCO-PA, and allows a single-pin antenna interface for both TX and RX modes; and 3) a push-pull LNA with passive gain boosting that reduces power consumption. Fabricated in 65nm CMOS, the RFE occupies merely 0.17mm². By scaling the supply voltage, the standalone VCO-PA exhibits a 20.8% (10.2%) power efficiency when delivering OdBm (-10dBm) output. The LNA shows lldB gain and 6.8dB NF while consuming 174pW.

Research lead: Masoud Babaie. In this reseach work we have proposed a new class of operation of an RF oscillator that minimizes its phase noise. The main idea is to enforce a clipped voltage waveform around the LC tank by increasing the second-harmonic of fundamental oscillation voltage through an additional impedance peak, thus giving rise to a class-F2 operation. As a result, the noise contribution of the tail current transistor on the total phase noise can be significantly decreased without sacrificing the oscillator's voltage and current efficiencies. Furthermore, its special impulse sensitivity function(ISF) reduces the phase sensitivity to thermal circuit noise. The prototype of the class-F2 oscillator is implemented in standard TSMC 65 nm CMOS occupying 0.2 mm2. It draws 32–38 mA from 1.3 V supply. Its tuning range is 19% covering 7.2–8.8 GHz. It exhibits phase noise of 139 dBc/Hz at 3 MHz offset from 8.7 GHz carrier, translated to an average figure-of-merit of 191 dBc/Hz with less than 2 dB variation across the tuning range. The long term reliability is also investigated with estimated ›10 year lifetime [IEEE Xplore link (Open Access)] [IEEE Xplore link][IEEE Xplore link] .

Research lead: Massoud Tohidian. A discrete-time IIR low-pass filter that achieves a high-order of filtering through a charge-sharing rotation. Its sampling rate is then multiplied through pipelining. The first stage of the filter can operate in either a voltage-sampling or charge-sampling mode. It uses switches, capacitors and a simple gm-cell, rather than opamps, thus being compatible with digital nanoscale technology. In the voltage-sampling mode, the gm-cell is bypassed so the filter is fully passive. A 7th-order filter prototype operating at 800 MS/s sampling rate is implemented in TSMC 65 nm CMOS. Bandwidth of this filter is programmable between 400 kHz to 30 MHz with 100 dB maximum stop-band rejection. Its IIP3 is +21 dBm and the averaged spot noise is 4.57 nV. [IEEE Xplore link (Open Access)] [IEEE Xplore link]

Research lead: Dr. Morteza Alavi. This research work proposes a wideband 2x13-bit in-phase/quadrature-phase (I/Q) RF digital-to-analog converter-based alldigital modulator realized in 65-nm CMOS. The isolation between I and Q paths is guaranteed employing 25% duty-cycle differential quadrature clocks. With a 1.3-V supply and an on-chip power combiner, the digital I/Q transmitter provides more than 21-dBm RF output power within a frequency range of 1.36–2.51 GHz. The peak RF output power, overall system, and drain efficiencies of the modulator are 22.8 dBm, 34%, and 42%, respectively. The measured static noise floor is below 160 dBc/Hz. The digital I/Q RF modulator demonstrates an IQ image rejection and local oscillator leakage of 65 and 68 dBc, respectively. It could be linearized using either of the two digital predistortion (DPD) approaches: a memoryless polynomial or a lookup table. Its linearity is examined using single-carrier 4/16/64/256/1024 quadrature amplitude modulation(QAM), as well as multi-carrier 256-QAM orthogonal frequency division multiplexing baseband signals while their related modulation bandwidth can be as high as 154 MHz. Employing DPD improves the third-order intermodulation product (IM ₃) by more than 25 dB, while the measured error vector magnitude for a “single-carrier 22-MHz 64-QAM” signal is better than 28 dB. This project is funded by STW in both phase I & II. [IEEE Xplore link (Open Access)]

"A Low Phase Noise Oscillator Principled on Transformer-Coupled Hard Limiting"

Research lead: Akshay Visweswaran. Reduced phase noise conversion in a monolithic oscillator suitable for basestation applications is realized by hard limiting and subsequently restoring the resonating waveform. Overdriven transistors hard limit the drain voltage swing and it is shown analytically that this desensitizes the oscillation phase to circuit noise. A pair of tuned, 1:2 step-up transformers in the feedback path restore the fundamental frequency component with sufficient gain to overdrive the transistors forming the oscillator core, with greater selectivity than an equivalent LC tank. The 8 GHz, 65 nm CMOS oscillator prototype targeting the GSM-900 base-station specification consumes 32 mA from 1.5 V. Normal-ized to 915 MHz, the phase noise measured at 1 MHz offset is –147.7 dBc/Hz, validating predictions from theory and simulation. The measured frequency pushing is less than 16 MHz/V [IEEE Xplore link].

Research lead: Masoud Babaie. An oscillator topology demonstrating an improved phase noise performance is proposed in this paper. It exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The proposed oscillator is based on enforcing a pseudo-square voltage waveform around the LC tank by increasing the third-harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled resonating windings. As a result, the effective impulse sensitivity function (ISF) decreases thus reducing the oscillator’s effective noise factor such that a significant improvement in the oscillator phase noise and power efficiency are achieved. A com-prehensive study of circuit-to-phase-noise conversion mechanisms of different oscillators’ structures shows the proposed class-F exhibits the lowest phase noise at the same tank’s quality factor and supply voltage. The prototype of the class-F oscillator is im- plemented in TSMC 65-nm standard CMOS. It exhibits average phase noise of 136 dBc/Hz at 3 MHz offset from the carrier over 5.9–7.6 GHz tuning range with figure-of-merit of 192 dBc/Hz. The oscillator occupies 0.12 mm while drawing 12 mA from 1.25 V supply. [IEEE Xplore link (Open Access)].

Research lead: Massoud Tohidian. An ultra-low phase noise oscillator is proposed. The basis of the proposed idea is that coupling a second oscillator core reduces the overall phase noise by 3 dB. For each core, a high-swing class-C oscillator is used to have the lowest phase noise. The oscillator is tunable from 4.07-4.91 GHz, drawing 39-59 mA from a 2.15 V power supply. The measured phase noise is -146.7 dBc/Hz and -163.1 dBc/Hz at 3 MHz and 20 MHz offset from a 4.07 GHz carrier, respectively. This is the lowest ever reported phase noise in bulk CMOS IC. This phase noise meets GSM900 normal basestation receiver and mobile station transmitter standards, which have the toughest phase noise requirements in cellular communications. [IEEE Xplore link]

Research lead: Iman Madadi. A highly reconfigurable superheterodyne receiver that employs a 3rd-order complex IQ charge-sharing band-pass filter (BPF) for image rejection and 1st-order feedback based RF-BPF for channel selection filtering. The operating RF input frequency of the receiver is 500 MHz—1.4 GHz with varying high-IF range of 33—93 MHz. All the gain stages are merely inverter-based g_m stages. The total gain of the receiver is 35 dB and in-band IIP3 at mid-gain is +10 dBm. The NF of the receiver is 6.7 dB, which is acceptable for the receiver without an LNA. The architecture is highly reconfigurable and follows the technology scaling. The RX occupies 0.47mm² of active area and consumes 24.5mA at 1.2V power supply [IEEE Xplore link] .

Research lead: Mohammadreza Mehrpoo. To achieve ultimately flexible multi-core radio operation, wide-band receiver RF front-ends must be robust against interference well in excess of the requirements usually specified by a radio standard. In this paper, a highly selective, very linear low-noise transconductance amplifier (LNTA) capable of large-signal handling for current-mode receiver (RX) front-ends is proposed and implemented in 65-nm CMOS. It is shown that by combining on-chip high-Q bandpass filters with a push/pull class-AB common-gate stage, a measured 1-dB desensitization point (B_1dB) and large-signal IIP3 of +8 dBm and +20 dBm, respectively, can be achieved. In addition, by applying a noise cancellation technique, via an auxiliary push/pull class-AB commonsource stage, the proposed LNTA measures a moderate NF of 5.9 dB, which is a very competitive number for such high value of B_1dB. The circuit consumes 7.5 mA at 1.5 V [IEEE Xplore link].

Research lead: Amir Reza Ahmadi Mehr. A two-channel RF generation system for a 2 GHz basestation transmitter that avoids pulling due to various parasitic coupling paths, especially between a strong RF output and an LC-tank of an RF oscillator. This is achieved through a fractional frequency translation by means of a programmable fractional divider realized as a dynamic edge selector of eight oscillator phases. This way, the integer harmonic frequency relationship of victims/aggressors within and between the RF transmission channels are avoided, thus rendered harmless in the creation of injection pulling spurs. The proposed method can reduce the injection pulling spur to -99 dBc and has been verified in a 65-nm CMOS testchip that occupies 0.561.46 mm2 area and emits -156 dBc/Hz noise floor. An RF oscillator is realized as a class-C topology without the bias current source [IEEE Xplore link].