### Conferences

#### 2017

[1] Y. Hu, T. Siriburanon, and **R. B. Staszewski,** “A 30-GHz class-F_{23} oscillator in 28nm CMOS using harmonic extraction and achieving 120kHz 1/f^{3} corner,” *Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), *sec. A4L-C1, pp. x–x, 12 Sept. 2017, Leuven, Belgium. (accepted)

[2] F.-W. Kuo, S. Pourmousavian, T. Siriburanon, R. Chen, L.-C. Cho, C.-P. Jou, F.-L. Hsueh, and **R. B. Staszewski,** “A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS,” *Proc. of IEEE Symp. on VLSI Circuits (VLSI), 7 June 2017, *sec. C14.1, pp. 178–179, Kyoto, Japan.

[3] L.-C. Cho, F.-W. Kuo, R. Chen, J. Liu, C.-P. Jou, F.-L. Hsueh, and **R. B. Staszewski,** “A 4GHz clock distribution architecture using subharmonically injection-locked coupled oscillators with clock skew calibration in 16nm CMOS,” *Proc. of IEEE Symp. on VLSI Circuits (VLSI), 7 June 2017, *sec. 10.4, pp. 130–131, Kyoto, Japan.

[4] H. Wang, F. Schembari, **R. B. Staszewski,** and M. Miskowicz, “Frequency-domain adaptive-resolution level-crossing sampling ADC,” *Proc. of IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017),24 May 2017,* pp. 1–4, Funchal, Madeira, Portugal.

[5] V. Nguyen, F. Schembari, and **R. B. Staszewski,** “Oscillator-based ADCs: An exploration of time-mode analog-to-digital conversion,” *Proc. of IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017), 24 May 2017,* pp. 1–4, Funchal, Madeira, Portugal.

[6] F. Zhang, P. Chen, A. Zhu, and **R. B. Staszewski**, “A highly power-efficient digital mixing RFDAC,” *Proc. of Research Colloquium of Royal Irish Academy (RIA) on Radio Science and Communications for a Smarter World, *ssec. 1.2, pp. 1–4, 9 Mar. 2017, Dublin, Ireland.

[7] Y.-H. Liu, V. K. Purushothaman, C. Lu, J. Dijkhuis, **R. B. Staszewski**, C. Bachmann and K. Philips, “A 770pJ/b 0.85V 0.3mm^{2} DCO-based phase-tracking RX featuring direct demodulation and data-aided carrier tracking for IoT applications,” * Proc. of IEEE Solid-State Circuits Conf.(ISSCC)*, sec. 24.1, pp. 408–409, 8 Feb. 2017, San Francisco, CA, USA. DOI:10.1109/ISSCC.2017.7870434. [IEEE Xplore link]

[8] C.-C. Li, M.-S. Yuan, C.-H. Chang, Y.-T. Lin, K. Hsieh, M. Chen, **R. B. Staszewski**, “A 0.2V trifilar-coil DCO with an energy harvesting DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution and frequency pushing of 38MHz/V, ” * Proc. of IEEE Solid-State Circuits Conf. (ISSCC), *sec. 19.6, pp. 332–333, 8 Feb. 2017, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2017.7870396. [IEEE Xplore link]

[9] E. Charbon, F. Sebastiano, M. Babaie, A. Vladimirescu, M. Shahmohammadi, **R. B. Staszewski**, H. A.R. Homulle, B. Patra, J. P.G. van Dijk, R. M. Incandela, L. Song, and B. Valizadehpasha, “Cryo-CMOS circuits and systems for scalable quantum computing, ” * Proc. of IEEE Solid-State Circuits Conf. (ISSCC), *sec. 15.5, pp. 264–265, 7 Feb. 2017, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2017.7870362. [IEEE Xplore link]

#### 2016

[10] M. Keshavarz Hedayati, A. Abdipour, R. S. Shirazi, M. John, M. J. Ammann, and **R. B. Staszewski**, “A 38 GHz on-chip antenna in 28-nm CMOS using artificial magnetic conductor for 5G wireless systems,” *Proc. of IEEE Millimeter-Wave and Terahertz Technologies Conf. (MMWATT), *ses. 7B, pp. 1–4, 21 Dec. 2016, Tehran, Iran. DOI:
10.1109/MMWaTT.2016.7869869. [IEEE Xplore link]

[11] Y. Wu, M. Shahmohammadi, Y. Chen, P. Lu, and **R. B. Staszewski**, “A 3.5–6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH TDC for low in-band phase noise, ” *Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), *sec. A3L-J4, pp. 356–359, 13 Sept. 2016, Lausanne, Switzerland. DOI: 10.1109/ESSCIRC.2016.7598279. [IEEE Xplore link]

[12] C.-C. Li, T.-H. Tsai, M.-S. Yuan, C.-C. Liao, C.-H. Chang, T.-C. Huang, H.-Y. Liao, C.-T. Lu, H.-Y. Kuo, K. Hsieh, M. Chen, A. Ximenes, and **R. B. Staszewski**, “A 0.034mm2, 725fs rms Jitter, 1.8%/V frequency-pushing, 10.8–19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS,” *Proc. of IEEE Symp. on VLSI Circuits (VLSI), *sec. 22.5, pp. 240–241, 17 June 2016, Honolulu, HI, USA. DOI: 10.1109/VLSIC.2016.7573551. [IEEE Xplore link]

[13] F.-W. Kuo, S. Binsfeld Ferreira, M. Babaie, R. Chen, L.-C. Cho, C.-P. Jou, F.-L. Hsueh, G. Huang, I. Madadi, M. Tohidian, and **R. B. Staszewski**, “A Bluetooth Low-Energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter,” *Proc. of IEEE Symp. on VLSI Circuits (VLSI), *sec. 7.1, pp. 64–65, 15 June 2016, Honolulu, HI, USA. DOI: 10.1109/VLSIC.2016.7573480. [IEEE Xplore link]

[14] Y. Wu and **R. B. Staszewski**, “A 0.5ps 1.4mW 50MS/s Nyquist bandwidth time-amplifier based two-step flash-time-to-digital converter,” *Proc. of IEEE International Nordic-Mediterranean Workshop on Time-to-Digital Converters and Applications (NoMe - TDC 2016), *pp. 1–4, 15 June 2016, Krakow, Poland. DOI: 10.1109/EBCCSP.2016.7605282. [IEEE Xplore link]

[15] P. Chen and **R. B. Staszewski**, “Exponential extended flash time-to-digital converter,” *Proc. of IEEE International Nordic-Mediterranean Workshop on Time-to-Digital Converters and Applications (NoMe - TDC 2016), *pp. 1–4, 15 June 2016, Krakow, Poland. DOI: 10.1109/EBCCSP.2016.7605281. [IEEE Xplore link]

[16] Z. Hu, L.C.N. de Vreede, M. S. Alavi, D. A. Cavillo-Cortes, **R. B. Staszewski**, and S. He, “A 5.9 GHz RFDACbased outphasing power amplifier in 40-nm CMOS with 49.2% efficiency and 22.2 dBm power,” *Proc. of IEEE Radio Frequency Integrated Circuits (RFIC) Symp., *sec. RMO3D-3, pp. 206–209, 23 May 2016, San Francisco, CA, USA. DOI: 10.1109/RFIC.2016.7508287. [IEEE Xplore link]

#### 2015

[17] F.-W. Kuo, M. Babaie, R. Chen, K. Yen, J.-Y. Chien, L. Cho, F. Kuo, C.-P. Jou, F.-L. Hsueh, and **R. B. Staszewski**, “A fully integrated 28nm Bluetooth low-energy transmitter with 36% system efficiency at 3dBm,” * Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), *sec. C2L-B, pp. 356–359, 17 Sept. 2015, Graz, Austria. DOI: 10.1109/ESSCIRC.2015.7313901. [IEEE Xplore link]

[18] P. Chen, X. Huang, Y.-H. Liu, M. Ding, C. Zhou, A. Ba, K. Philips, H. de Groot, and ** R. B. Staszewski**, “Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs,” * Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), *sec. B5L-A, pp. 283–286, 16 Sept. 2015, Graz, Austria.DOI: 10.1109/ESSCIRC.2015.7313882. [IEEE Xplore link]

[19] I. Madadi, M. Tohidian, K. Cornelissens, P. Vandenameele, and **R. B. Staszewski**, “A TDD/FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28nm CMOS,” * Proc. of IEEE Symp. on VLSI Circuits (VLSI), *sec. 22.4, pp. C08–C09, 19 June 2015, Kyoto, Japan. DOI: 10.1109/VLSIC.2015.7231302. [IEEE Xplore link]

[20] P. Chen, X.-C. Huang, and **R. B. Staszewski**, “Fractional spur suppression in all-digital phase-locked loops,” * Proc. of IEEE Intl. Symp. on Circuits and Systems (ISCAS), paper 2597,*sec. C4L-B, pp. 2565–2568, 27 May 2015, Lisbon, Portugal. DOI: 10.1109/ISCAS.2015.7169209. [IEEE Xplore link]

[21] B. Wang, Y.-H. Liu, P. Harpe, J. vd Heuvel, B. Liu, H. Gao, P. Baltus, and **R. B. Staszewski**, “A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS,” * Proc. of IEEE Intl. Symp. on Circuits and Systems (ISCAS), paper 1509, *sec. C2P-V, pp. 2289–2292, 27 May 2015, Lisbon, Portugal. DOI: 10.1109/ISCAS.
2015.7169140. [IEEE Xplore link]

[22] X. Luo, H. Qian, and **R. B. Staszewski**, “A waveform-shaping millimeter-wave oscillator with 184.7dBc/Hz FOM in 40nm digital CMOS process,” * Proc. of 2015 IEEE International Microwave Symp. (IMS), *sec. TU4H-1, pp. 1–3, 19 May 2015, Phoenix, Arizona, USA. [IEEE Xplore link]

[23] A. Tavakol and **R. B. Staszewski**, “An CMOS impedance sensor for MEMS adaptive antenna matching,” * Proc. of IEEE Radio Frequency Integrated Circuits (RFIC) Symp., *sec. RTU–IF6-2, pp. 379–382, 19 May 2015, Phoenix, Arizona, USA. DOI: 10.1109/RFIC.2015.7337784. [IEEE Xplore link]

[24] Z. Zong, M. Babaie, and **R. B. Staszewski**, “A 60 GHz 25% tuning range frequency generator with implicit divider based on third harmonic extraction with 182 dBc/Hz FoM,” * Proc. of 2015 IEEE Radio Frequency Integrated Circuits (RFIC) Symp.,* sec. RTU-1-A-5, pp. 279–282, 18 May 2015, Phoenix, Arizona, USA. DOI: 10.1109/RFIC.2015.7337759. [IEEE Xplore link]

[25] M. Babaie, ** R. B. Staszewski**, L. Galatro, and M. Spirito, “A wideband 60 GHz class-E/F2 power amplifier in 40nm CMOS,” * Proc. of IEEE Radio Frequency Integrated Circuits (RFIC) Symp., *sec. RMO-4-B-4, pp. 215–218, 18 May 2015, Phoenix, Arizona, USA. DOI: 10.1109/RFIC.2015.7337743. [IEEE Xplore link]

[26] M. Babaie, M. Shahmohammadi, and **R. B. Staszewski**, “A 0.5V 0.5mW switching current source oscillator,” * Proc. of 2015 IEEE Radio Frequency Integrated Circuits (RFIC) Symp.,* sec.RMO-4-A-1, pp. 183–186, 18 May, Phoenix, Arizona, USA.DOI: 10.1109/RFIC.2015.7337735. [IEEE Xplore link]

[27] Y. Wu, P. Lu, and **R. B. Staszewski**, “A 103fs_{rms} 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-time-todigital converter for ADPLL,”* Proc. of 2015 IEEE Radio Frequency Integrated Circuits (RFIC) Symp.,* sec. RMO-2-C-2, pp. 95–98, 18 May 2015, Phoenix, Arizona, USA. DOI: 10.1109/RFIC.2015.7337713. [IEEE Xplore link]

[28] M. Shahmohammadi, M. Babaie, and **R. B. Staszewski**, “A 1/f noise upconversion reduction technique applied to class-D and class-F oscillators,” * Proc. of IEEE Solid-State Circuits Conf. (ISSCC), *sec. 25.4, pp. 444–445, 25 Feb. 2015, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2015.7063117.[IEEE Xplore link]

[29] T.-H. Tsai, M.-S. Yuan, C.-H. Chang, C.-C. Liao, C.-C. Li, and **R. B. Staszewski**, “A 1.22ps integrated-jitter 0.25- to-4GHz fractional-N ADPLL in 16nm FinFET CMOS,” *Proc. of IEEE Solid-State Circuits Conf. (ISSCC), *sec. 14.5, pp. 260–261, 24 Feb. 2015, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2015.7063025.[IEEE Xplore link]

#### 2014

[30] I. E. Lager, **R. B. Staszewski**, A. B. Smolders, and D.M.W. Leenaerts, “Ultra-high data-rate wireless transfer in a saturated spectrum - new paradigms,” *Proc. of IEEE European Microwave Week (EuMW) Conference,* sec. EuMC47, pp. 917–920,, 9 Oct. 2014, Fiera di Roma, Italy. [IEEE Xplore link]

[31] W. Wu, **R. B. Staszewski**, and J. R. Long, “Design for test of a mm-wave ADPLL-based transmitter,” (Invited), *Proc. of IEEE Custom Integrated Circuits Conf. (CICC),* ses. 14–1, pp. 1–8, 16 Sept. 2014, San Jose, CA, USA. [IEEE Xplore link]

[32] A. Visweswaran, J. R. Long, and **R. B. Staszewski**, “A 1.2V 110-MHz-UGB differential class-AB amplifier in 65nm CMOS,” *Proc. of IEEE Custom Integrated Circuits Conf. (CICC),* ses. 8–4, pp. 1–4, 16 Sept. 2014, San Jose, CA, USA.[IEEE Xplore link]

[33] F.-W. Kuo, R. Chen, K. Yen, H.-Y. Liao, C.-P. Jou, F.-L. Hsueh, M. Babaie, and **R. B. Staszewski**, “A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS,” *Proc. of 2005 IEEE Symp. on VLSI Circuits (VLSI),* sec. 9.4, pp. 1–2, 12 June 2014, Honolulu, USA. [IEEE Xplore link]

[34] A. Ba, V. K. Chillara, Y. Liu, K. Philips, and **R. B. Staszewski**, “A 2.4GHz class-D power amplifier with conduction angle calibration for -50dBc harmonic emissions,” *Proc. of 2014 IEEE Radio Frequency Integrated Circuits (RFIC) Symp.,* sec. RMO4B-3, pp. 239–242, 2 June 2014, Tampa, Florida, USA. [IEEE Xplore link]

[35] V. K. Chillara, Y.-H. Liu, B. Wang, A. Ba, M. Vidojkovic, K. Philips, H. de Groot, and **R. B. Staszewski**, “An 860µW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications,” *Proc. of IEEE Solid-State Circuits Conf. (ISSCC),* sec. 9.8, pp. 172–173, 11 Feb. 2014, San Francisco, CA, USA. [IEEE Xplore link]

[36] M. Tohidian, I. Madadi and **R. B. Staszewski**, “A fully integrated highly reconfigurable discrete-time super-heterodyne receiver,” *Proc. of IEEE Solid-State Circuits Conf. (ISSCC)*, sec. 3.8, pp. 72–73, 10 Feb. 2014, San Francisco, CA, USA.[IEEE Xplore link]

#### 2013

[37] S.A.R.A. Mehr, M. Tohidian, and **R. B. Staszewski**, “Frequency translation through fractional divider for two-channel pulling mitigation,”* Proc. of IEEE 2013 European Solid-State Circuits Conference (ESSCIRC’13)*, sec. B3L-D, pp. 241–244, 18 Sept. 2013, Bucharest, Romania. [IEEE Xplore link]

[38] J.-C. Zhuang and **R. B. Staszewski**, “Gain estimation of a digital-to-time converter for phase-prediction all-digital PLL,” *Proc. of IEEE 21th European Conference on Circuit Theory and Design (ECCTD’13)*, paper 122, pp. 1–4, 11 Sept. 2013, Dresden, Germany. [IEEE Xplore link]

[39] M. Babaie and **R. B. Staszewski**, “A study of RF oscillator reliability in nanoscale CMOS,” *Proc. of IEEE 21th European Conference on Circuit Theory and Design (ECCTD’13)*, paper 114, pp. 1–4, 11 Sept. 2013, Dresden, Germany. [IEEE Xplore link]

[40] I. Madadi, M. Tohidian, and **R. B. Staszewski**, “A 65nm CMOS High-IF Superheterodyne Receiver with a High-Q Complex BPF,”* Proc. of 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symp. *, sec. RTU2A–3, pp. 323–326, 4 June 2013, Seattle, USA. [IEEE Xplore link]

[41] M. Tohidian, S.A.R.A. Mehr, and **R. B. Staszewski**, “Dual-Core High-Swing Class-C Oscillator with Ultra-Low Phase Noise,”* Proc. of 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symp. *, sec. RMO4C–4, pp. 243–246, 3 June 2013, Seattle, USA. [IEEE Xplore link]

[42] A. Visweswaran, J. R. Long, L. Galatro, M. Spirito, and **R. B. Staszewski**, “An FM Demodulator Operating Across 2-10GHz IF,”* Proc. of 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symp. *, sec. RMO4A–1, pp. 213–216, 3 June 2013, Seattle, USA. [IEEE Xplore link]

[43] M. Mehrpoo and **R. B. Staszewski**, “A Highly Selective LNTA Capable of Large-Signal Handling for RF Receiver Front-End,”* Proc. of 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symp. *, sec. RMO3B–4, pp. 185–188, 3 June 2013, Seattle, USA. [IEEE Xplore link]

[44] M. S. Alavi, G. Voicu, **R. B. Staszewski**, L.C.N. de Vreede, and J. R. Long, “A 12-bit Digital I/Q RF-DAC in 65-nm CMOS,”* Proc. of 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symp. *, sec. RMO3A–5, pp. 167–170, 3 June 2013, Seattle, USA. **This paper received The Best Student Paper Award- 2^{nd} Place.** [IEEE Xplore link]

[45] W. Wu, X. Bai, **R. B. Staszewski**, and J. R. Long, “A mm-Wave FMCW Radar Transmitter Based on a Multirate ADPLL,”* Proc. of 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symp. *, sec. RMO2C–1, pp. 107–110, 3 June 2013, Seattle, USA. [IEEE Xplore link]

[46] M. Babaie, A. Visweswaran, Z. He, and **R. B. Staszewski**, “Ultra-Low Phase Noise 7.2-8.7 GHz Clip-and-Restore Oscillator with 191 dBc/Hz FoM,”* Proc. of 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symp. *, sec. RMO1C–5, pp. 43–46, 3 June 2013, Seattle, USA. [IEEE Xplore link]

[47] W. Wu, X. Bai, **R. B. Staszewski**, and J. R. Long, “A 56.4-63.4GHz spuriousfree all-digital fractional-N PLL in 65nm CMOS,”* Proc. of IEEE Solid-State Circuits Conf. (ISSCC) *, sec. 20.4, pp. 352–353, 20 Feb. 2013, San Francisco, CA, USA. [IEEE Xplore link]

[48] M. Babaie, and **R. B. Staszewski**, “Third-harmonic injection technique applied to a 5.87-to-7.56GHz 65nm CMOS class-F oscillator with 192dBc/Hz FoM,”* Proc. of IEEE Solid-State Circuits Conf. (ISSCC) *, sec. 20.2, pp. 348–349, 20 Feb. 2013, San Francisco, CA, USA. [IEEE Xplore link]

[49] J.-W. Lai, C.-H. Wang, K. Kao, A. Lin, Y.-H. Cho, L. Cho, M.-H. Hung, X.-Y. Shih, C.-M. Lin, S.-H. Yan, Y.-H. Chung, P. Liang, G.-K. Deng, H.-S. Li, G. Chien, and **R. B. Staszewski**, “A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency class-D DPA in 40nm CMOS,”* Proc. of IEEE Solid-State Circuits Conf. (ISSCC)*, sec. 19.8, pp. 342–343, 20 Feb. 2013, San Francisco, CA, USA. [IEEE Xplore link]

[50] M. Tohidian, I. Madadi, and **R. B. Staszewski**, “A 2mW 800MS/s 7th-order discrete-time IIR filter with 400kHz-to-30MHz BW and 100dB stop-band rejection in 65nm CMOS,”* Proc. of IEEE Solid-State Circuits Conf. (ISSCC) *, sec. 10.2, pp. 174–175, 19 Feb. 2013, San Francisco, CA, USA. [IEEE Xplore link]

#### 2012

[51] P. Kumar, E. Charbon, **R. B. Staszewski**, and A. Borowski, “Low power timeof-light 3D imager system in standard CMOS,” *Proc. of 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS’12),* ses. C4L-A, pp. 941–944, Seville, Spain, Dec. 2012. [IEEE Xplore link]

[52] J. Zhuang, and **R. B. Staszewski**, “A low-power all-digital PLL architecture based on phase prediction,” *Proc. of 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS’12),* ses. C2L–A, pp. 797–800, Seville, Spain, Dec. 2012. [IEEE Xplore link]

[53] W. Jiang, A. Tavakol, P. Effendrik, M. van de Gevel, F. Verwaal, and **R. B. Staszewski**, “Design of ADPLL system for WiMAX applications in 40-nm CMOS,” *Proc. of 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS’12),* ses. A1L–D, pp. 73–76, Seville, Spain, Dec. 2012. [IEEE Xplore link]

[54] A. Visweswaran, **R. B. Staszewski**, J. R. Long, and A. Akhnoukh, “Fine frequency tuning using injection-control in a 1.2V 65nm CMOS quadrature oscillator,” *Proc. of 2012 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., *sec. RTU1A–1, pp. 293–;296, 19 June 2012, Montreal, Canada. [IEEE Xplore link]

[55] W. Wu, J. R. Long, **R. B. Staszewski**, and J. J. Pekarik, “High-resolution 60-GHz DCOs with reconfigurable distributed metal capacitors in passive resonators,” *Proc. of 2012 IEEE Radio Frequency Integrated Circuits (RFIC) Symp.,* sec. RMO2A–5, pp. 91–94, 18 June 2012, Montreal, Canada. [IEEE Xplore link]

[56] A. Visweswaran, **R. B. Staszewski**, and J. Long, “A clip-and-restore technique to reduce phase noise in a 1.2V 65nm CMOS oscillator for cellular mobile and basestation applications,”* Proc. of IEEE Solid-State Circuits Conf., *sec. 20.5, pp. 350–351, 22 Feb. 2012, San Francisco, CA, USA. [IEEE Xplore link]

#### 2011

[57] J. Mehta, **R. B. Staszewski**, G. Feygin, O. Eliezer, M. Frechette, and P. Balsara, “Mismatch considerations in an RF–DAC design for a digital polar EDGE transmitter,” *Proc. of IEEE Symp. on Radio-Frequency Integration Technology (RFIT) Conf.,* sec. FR1A–4, pp. 169–172, 2 Dec. 2011, Beijing, China. [IEEE Xplore link]

[58] **R. B. Staszewski** and M. S. Alavi, “Digital I/Q RF transmitter using time-division duplexing,” *Proc. of IEEE Symp. on Radio-Frequency Integration Technology (RFIT) Conf.,* sec. FR1A–3, pp. 165–168, 2 Dec. 2011, Beijing, China. [IEEE Xplore link]

[59] M. S. Alavi, **R. B. Staszewski**, L. C.N. de Vreede, and J. R. Long, “Orthogonal summing and power combining network in a 65-nm all-digital RF I/Q modulator,” *Proc. of IEEE Symp. on Radio-Frequency Integration Technology (RFIT) Conf., *sec. TH1A–2, pp. 21–24, 1 Dec. 2011, Beijing, China. [IEEE Xplore link]

[60] **R. B. Staszewski**, “Digital RF and digitally-assisted RF (invited),” *Proc. of IEEE Symp. on Radio-Frequency Integration Technology (RFIT) Conf., *sec. K–2, pp. 9–16, 30 Nov. 2011, Beijing, China. [IEEE Xplore link]

[61] M. S. Alavi, A. Visweswaran, **R. B. Staszewski**, L. C. N. de Vreede, J. R. Long, and A. Akhnoukh, “A 2-GHz digital I/Q modulator in 65-nm CMOS,” *Proc. of IEEE Asian Solid-State Circuits Conf. (ASSCC),* sec. 11–3, pp. 277–280, 16 Nov. 2011, Jeju, Korea. [IEEE Xplore link]

[62] **R. B. Staszewski**, “Digital RF architectures for wireless transceivers (invited),” *Proc. of IEEE 20th European Conference on Circuit Theory and Design (ECCTD’11), *sec. PLEN4.1, pp. 438–445, Linkoping, Sweden, 30 Aug. 2011. [IEEE Xplore link]

[63] P. Effendrik, W. Jiang, M. van de Gevel, F. Verwaal, **R. B. Staszewski**, “Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS,” *Proc. of IEEE 20th European Conference on Circuit Theory and Design (ECCTD’11), *sec. T11.4, pp. 370–373, Linkoping, Sweden, 30 Aug. 2011. [IEEE Xplore link]

[64] **R. B. Staszewski**, I. Bashir, and K. Waheed, “Dynamic bandwidth adjustment of an RF all-digital PLL,” *Proc. of 2011 IEEE Radio Frequency Integrated Circuits (RFIC) Symp.,* sec. RMO4D-2, pp. 311–314, June 2011, Baltimore, MD, USA. [IEEE Xplore link]

[65] O. Eliezer, **B. Staszewski** and S. Vemulapalli, “Digitally controlled oscillator in a 65nm GSM/EDGE transceiver with built-in compensation for capacitor mismatches,” *Proc. of 2011 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., *sec. RTUIF–22, pp. 533–536, June 2011, Baltimore, MD, USA. [IEEE Xplore link]

[66] I. Bashir and **R. B. Staszewski**, “Autonomous predistortion calibration of an RF power amplifier,” *Proc. of 2011 IEEE Intl. Symp. on Circuits and Systems, paper 2197, *sec. A1L-L, pp. 205–208, 16 May 2011, Rio de Janeiro, Brazil. [IEEE Xplore link]

[67] **R. B. Staszewski**, “All-digital RF frequency modulation,” *Proc. of 2011 IEEE Intl. Symp. on Circuits and Systems, paper 2475, *sec. A2L–J, pp. 426–429, 16 May 2011, Rio de Janeiro, Brazil. [IEEE Xplore link]

[68] **R. B. Staszewski**, K. Waheed, S. Vemulapalli, F. Dulger, J. Walberg, C.-M. Hung, and O. Eliezer, “Spur-free all-digital PLL in 65nm for mobile phones,” *Proc. of IEEE Solid-State Circuits Conf., *sec. 3.1, pp. 52–53, Feb. 2011, San Francisco, CA, USA. [IEEE Xplore link]

#### 2010

[69] O. Eliezer,**B. Staszewski**, J. Mehta, F. Jabbar, and I. Bashir, “Accurate self-characterization of mismatches in a capacitor array of a digitally-controlled oscillator,”* Proc. of IEEE Dallas Circuits and Systems Workshop (DCAS–10): Design Automation, Methodologies and Manufacturability, *pp. 1–4, Oct. 2010, Dallas, TX, USA. [IEEE Xplore link]

[70] J. Mehta, I. Bashir, V. Zoicas, Y. Wang, O. Eliezer, K. Waheed, M. Entezari, S. Larson, D. Shrestha, S. Rezeq, **R. B. Staszewski**, and P. Balsara, “Self-calibration of a power pre-amplifier in a digital polar transmitter,” *Proc. of IEEE Dallas Circuits and Systems Workshop (DCAS-10): Design Automation, Methodologies and Manufacturability, *pp. 1–4, Oct. 2010, Dallas, TX, USA. [IEEE Xplore link]

[71] K. Waheed, M. Sheba, **R. B. Staszewski**, F. Dulger and S.D. Vamvakos, “Spurious free time-to-digital conversion in an ADPLL using short dithering sequences,” *Proc. of 2010 IEEE Custom Integrated Circuits Conf.,* sec. 12.6 pp. 1–4, Sept. 2010, San Jose, CA, USA. [IEEE Xplore link]

[72] O. Eliezer, **R. B. Staszewski**, and D. Mannath, “A statistical approach for design and testing of analog circuitry in low-cost SoCs,” *Proc. of 53rd IEEE Int'l Midwest Symp. on Circuits and Systems,* session B1L–B, pp. 461–464, Aug. 2010, Seattle, WA, USA. [IEEE Xplore link]

[73] **R. B. Staszewski**, “State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS,” *Proc. of 2010 IEEE Intl. Symp. on Circuits and Systems, *sec. 16.9, pp. 229–232, May 2010, Paris, France. [IEEE Xplore link]

[74] **R. B. Staszewski**, S. Vemulapalli, and K. Waheed, “An all-digital offset PLL architecture,” *Proc. of 2010 IEEE Radio Frequency Integrated Circuits (RFIC) Symp.,* sec. RMO1A-3, pp. 17–20, May 2010, Anaheim, CA, USA. [IEEE Xplore link]

[75] I. Bashir, **R. B. Staszewski**, O. Eliezer, K. Waheed, V. Zoicas, N. Tal, J. Mehta, M.-C. Lee, P. T. Balsara, and B. Banerjee, “An EDGE transmitter with mitigation of oscillator pulling,” *Proc. of 2010 IEEE Radio Frequency Integrated Circuits (RFIC) Symp.,* sec. RMO1A–2, pp. 13–16, May 2010, Anaheim, CA, USA. [IEEE Xplore link]

[76] J. Mehta, **R. B. Staszewski**, O. Eliezer, S. Rezeq, K. Waheed, M. Entezari, G. Feygin, S. Vemulapalli, V. Zoicas, C.-M. Hung, N. Barton, I. Bashir, K. Maggio, M. Frechette, M.-C. Lee, J. Walberg, P. Cruise, and N. Yanduru, “A 0.8mm^{2} all-digital SAW-less polar transmitter in 65nm EDGE SoC,” *Proc. of IEEE Solid-State Circuits Conf.,* sec. 3.2, pp. 58–59, Feb. 2010, San Francisco, CA, USA. [IEEE Xplore link]

#### 2009

[77] W.-H. Wu, J. R. Long, and **R. B. Staszewski**, “A digital ultra-fast acquisition linear frequency modulated PLL for mm-wave FMCW radars,” *Proc. of IEEE Symp. on Radio-Frequency Integration Technology (RFIT) Conf.,* sec. TH1B–3, pp. 32–35, Dec. 2009, Singapore. [IEEE Xplore link]

[78] O. E. Eliezer, **R. B. Staszewski**, and P. T. Balsara, “A methodological approach for the minimization of self-interference effects in highly integrated transceiver SoCs,” *Proc. of IEEE Conf. on Microwaves, Communications, Antennas and Electronics Systems (COMCAS) Conf.,* pp. 1–4, Nov. 2009, Tel-Aviv, Israel. [IEEE Xplore link]

[79] **R. B. Staszewski**, K. Waheed, S. Vemulapalli, P. Vallur, M. Entezari, and O. Eliezer, “Elimination of spurious noise due to time-to-digital converter,”* Proc. of Eighth IEEE Dallas Circuits and Systems Workshop: Energy Efficient Circuits and Systems (DCAS–09),* pp. 67–70, Oct. 2009, Dallas, TX, USA. [IEEE Xplore link]

[80] K. Muhammad, C.-M. Hung, D. Leipold, T. Mayhugh, I. Elahi, I. Deng, C. Fernando, M.-C. Lee, T. Murphy, J. L. Wallberg, **R. B. Staszewski**, S. Larson, T. Jung, P. Cruise, V. Roussel, S. K. Vemulapalli, R. Staszewski, O. E. Eliezer, F. Feygin, K. Kunz, and K. Maggio, “A low-cost quad-band single-chip GSM/GPRS radio in 90nm digital CMOS,” *Proc. of 2009 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., *sec. RMO3A–4, pp. 197–200, June 2009, Boston, MA, USA. [IEEE Xplore link]

[81] I. Bashir, **R. B. Staszewski**, O. Eliezer, K. Waheed, and P. T. Balsara, “An SoC with automatic bias optimization of an RF oscillator,” Proc. of 2009 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO3D–3, pp. 259–262, June 2009, Boston, MA, USA. [IEEE Xplore link]

[82] J. Tangudu, S. Gunturi, S. Jalan, J. Janardhanan, R. Ganesan, D. Sahu, K. Waheed, J. Wallberg, and **R. B. Staszewski**, “Quantization noise improvement of Time to Digital converter (TDC) for ADPLL,” *Proc. of 2009 IEEE Intl. Symp. on Circuits and Systems,* pp. 1020–1023, May 2009, Taipei, Taiwan. [IEEE Xplore link]

#### 2008

[83] J. Lopez, D. Y. Lie, **R. B. Staszewski**, D. Huang, C.-M. Hung, and S. Swaminathan, “On the portability and performance of fully monolithic transformer structures for RF power amplfiers in standard CMOS process,” *Proc. of Seventh IEEE Dallas Circuits and Systems Workshop; SoC: Design, Application, Integration and Software (DCAS–08), *pp. 103–106, Oct. 2008, Dallas, TX, USA. [IEEE Xplore link]

[84] I. L. Syllaios, P. T. Balsara, and **R. B. Staszewski**, “Envelope and phase path recombination in ADPLL-based wideband polar transmitters,” *Proc. of Seventh IEEE Dallas Circuits and Systems Workshop; SoC: Design, Application, Integration and Software (DCAS–08),* pp. 111–114, Oct. 2008, Dallas, TX, USA. [IEEE Xplore link]

[85] O. Eliezer, **B. Staszewski**, S. Bhatara, I. Bashir, and P. T. Balsara, “Active mitigation of induced phase distortion in a GSM SoC,” *Proc. of 2008 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., *sec. RMO1A–3, pp. 17–20, June 2008, Atlanta, GA, USA. [IEEE Xplore link]

[86] K. Waheed, **R. B. Staszewski**, and S. Rezeq, “Curse of digital polar transmission: Precise delay alignment in amplitude and phase modulation paths,”* Proc. of 2008 IEEE Intl. Symp. on Circuits and Systems, *sec. 5.5, pp. 3142–3145, May 2008, Seattle, WA, USA. [IEEE Xplore link]

[87] K. Waheed and **R. B. Staszewski**, “Mitigation of CMOS device variability in the transmitter amplitude path using Digital RF Processing,” *Proc. of 2008 IEEE Intl. Symp. on Circuits and Systems, *sec. 18.7, pp. 568–571, May 2008, Seattle, WA, USA. [IEEE Xplore link]

[88] **R. B. Staszewski**, D. Leipold, O. Eliezer, M. Entezari, K. Muhammad, I. Bashir, C.-M. Hung, J. Wallberg, R. Staszewski, P. Cruise, S. Rezeq, S. Vemulapalli, K. Waheed, N. Barton, M.-C. Lee, C. Fernando, K. Maggio, T. Jung, I. Elahi, S. Larson, T. Murphy, G. Feygin, I. Deng, T. Mayhugh, Y.-C. Ho, K.-M. Low, C. Lin, J. Jaehnig, J. Kerr, J. Mehta, S. Glock, T. Almholt, and S. Bhatara, “A 24mm^{2} Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS,” *Proc. of IEEE Solid-State Circuits Conf., *sec. 10.5, pp. 208–209, 607, Feb. 2008, San Francisco, CA, USA. [IEEE Xplore link]

#### 2007

[89] **R. B. Staszewski**, “Modeling of an Electronic Noise and Media in a Magnetic Recording Read Channel Using VHDL,” *Proc. of Sixth IEEE Dallas Circuits and Systems Workshop; SoC: Design, Application, Integration and Software (DCAS–07),* pp. 113–116, Nov. 2007, Dallas, TX, USA. [IEEE Xplore link]

[90] **R. B. Staszewski**, “Top-Down Simulation Methodology of a Mixed-Signal Read Channel Using Standard VHDL,” *Proc. of Sixth IEEE Dallas Circuits and Systems Workshop; SoC: Design, Application, Integration and Software (DCAS-07), *pp. 109-112, Nov. 2007, Dallas, TX, USA. [IEEE Xplore link]

[91] E. Atalla, I. Bashir, P. Balsara, K. Kiasaleh, and **R. B. Staszewski**, “A Practical Step Forward Toward Software-Defined Radio Transmitters,” *Proc. of Sixth IEEE Dallas Circuits and Systems Workshop; SoC: Design, Application, Integration and Software (DCAS–07), *pp. 63–66, Nov. 2007, Dallas, TX, USA. [IEEE Xplore link]

[92] I. L. Syllaios, P. T. Balsara, and **R. B. Staszewski**, “Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications,”* Proc. of 2007 IEEE Custom Integrated Circuits Conf.,* sec. 27.6, pp. 861–864, Sept. 2007, San Jose, CA, USA. [IEEE Xplore link]

[93] I. L. Syllaios, P. T. Balsara, and **R. B. Staszewski**, “On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios,” *Proc. of 18th IEEE Annual International Symposium on Personal Indoor and Mobile Radio Communications (PIMRC 2007)., *no. 1106, pp. 1–6, Sept. 2007, Athens, Greece. [IEEE Xplore link]

[94] O. Eliezer, I. Bashir, **R. B. Staszewski**, and P. T. Balsara, “Built-in Self Testing of a DRP-Based GSM Transmitter,” *Proc. of 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., *sec. RMO4D-2, pp. 339–342, June 2007, Honolulu, HI, USA. [IEEE Xplore link]

[95] S. Akhtar, P. Litmanen, M. Ipek, J. (H.-C.) Lin , S. Pennisi, F.-J. Huang, and **R. B. Staszewski**, “Analog Path for Triple Band WCDMA Polar Modulated Transmitter in 90nm CMOS,” *Proc. of 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symp.,* sec. RMO3A-2, pp. 185–188, June 2007, Honolulu, HI, USA. [IEEE Xplore link]

[96] **R. B. Staszewski**, K. Muhammad, and O. Eliezer, “Digital RF Processor (DRP™) for Mobile Phones,” *Proc. of 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symp.,* sec. RMO3A–1, pp. 181–184, June 2007, Honolulu, HI, USA. [IEEE Xplore link]

[97] K. Waheed, **R. B. Staszewski**, and J. Wallberg, “Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation,” *Proc. of 2007 IEEE Intl. Symp. on Circuits and Systems,* sec. 5.5, pp. 3291–3294, May 2007, New Orleans, LA, USA. [IEEE Xplore link]

[98] K. Waheed and **R. B. Staszewski**, “Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS,” *Proc. of 2007 IEEE Intl. Symp. on Circuits and Systems, *sec. 19.3, pp. 1253–1256, May 2007, New Orleans, LA, USA. [IEEE Xplore link]

[99] R. Staszewski, T. Jung, **R. B. Staszewski**, D. Leipold, and T. Murphy, “Software Aspects of the Digital RF Processor (DRP™),” *Proc. of IEEE International Conf. on IC Design and Technology (ICICDT),* pp. 1–5, May/June. 2007, Austin, TX, USA. [IEEE Xplore link]

#### 2006

[100] W. Krenik and **R. B. Staszewski**, “Fully-integrated CMOS RF transceivers,” *Proc. of 2006 IEEE Asia-Pacific Microwave Conf. (APMC),* sec. FR4A–5, pp. 1795–1800, Dec. 2006, Yokohama, Japan. [IEEE Xplore link]

[101] **R. B. Staszewski**, J. Wallberg, and P. T. Balsara, “All-Digital PLL with Variable Loop Type Characteristics,” *Proc. of Fifth IEEE Dallas Circuits and Systems Workshop: Design, Application, Integration and Software (DCAS–06),* pp. 115–118, Oct. 2006, Dallas, TX, USA. [IEEE Xplore link]

[102] I. Bashir, **R. B. Staszewski**, and O. Eliezer, “Tuning Word Retiming of a Digitally-Controlled Oscillator Using RF Built-In Self Test,” *Proc. of Fifth IEEE Dallas Circuits and Systems Workshop: Design, Application, Integration and Software (DCAS–06),* pp. 103–106, Oct. 2006, Dallas, TX, USA. [IEEE Xplore link]

[103] S. D. Vamvakos, **R. B. Staszewski**, M. Sheba, and K. Waheed, “Noise Analysis of Time-to-Digital Converter in All-Digital PLLs,” *Proc. of Fifth IEEE Dallas Circuits and Systems Workshop: Design, Application, Integration and Software (DCAS–06),* pp. 87–90, Oct. 2006, Dallas, TX, USA. [IEEE Xplore link]

[104] O. Eliezer, O. Friedman, and **R. B. Staszewski**, “A built-in tester for modulation noise in a wireless transmitter,”

[105] **R. B. Staszewski**, K. Muhammad, and D. Leipold, “Digital RF processing techniques for SoC radios (invited),” *Proc. of 2006 IEEE Custom Integrated Circuits Conf., *sec. 27.1, pp. 789–796, Sept. 2006, San Jose, CA, USA. [IEEE Xplore link]

[106] **R. B. Staszewski**, K. Muhammad, and D. Leipold, “Digital Signal Processing for RF at 45-nm CMOS and Beyond,” *Proc. of 2006 IEEE Custom Integrated Circuits Conf.,* sec. 13.1, pp. 517–522, Sept. 2006, San Jose, CA, USA. [IEEE Xplore link]

[107] S. Akhtar, M. Ipek, J. (H.-C.) Lin , **R. B. Staszewski**, and P. Litmanen, “Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOS,” *Proc. of 2006 IEEE Custom Integrated Circuits Conf.,* sec. 7.4, pp. 129–132, Sept. 2006, San Jose, CA, USA. [IEEE Xplore link]

[108] R. Staszewski, T. Jung, **R. B. Staszewski**, K. Muhammad, D. Leipold, T. Murphy, S. Sabin, J. Wallberg, S. Larson, M. Entezari, J. Fresquez, S. Dondershine, and S. Syed, “Software Assisted Digital RF Processor for Single-Chip GSM Radio in 90 nm CMOS,” *Proc. of 2006 IEEE Custom Integrated Circuits Conf., *sec. 6.1, pp. 81–84, Sept. 2006, San Jose, CA, USA. [IEEE Xplore link]

[109] **B. Staszewski** and C.-M. Hung, “Frequency synthesis in a digital RF processor (DRP™) for mobile phones,” *Proc. of The Sixth Annual Emerging Information Technology Conf. (EITC 2006),* sec. T2, Aug. 2006, Dallas, TX, USA.

[110] **R. B. Staszewski**, P. Cruise, and D. Leipold, “Crystal Drift Compensation in a Mobile Phone,” Proc. of 2006 IET Irish Signals and Systems Conf., pp. 241–245, June 2006, Dublin, Ireland. [IEEE Xplore link]

[111] K. Muhammad, T. Murphy, and **R. B. Staszewski**, “Verification of RF SoCs: RF, analog, baseband and software,” *Proc. of 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., *sec. RTU1C–1, pp. 407–410, June 2006, San Francisco, CA, USA. [IEEE Xplore link]

#### 2005

[112] **R. B. Staszewski**, K. Muhammad, and D. Leipold, “Digital RF processor (DRP™) for cellular phones,”* Proc. of IEEE 23rd Norchip Conf.,* pp. 1–4, Nov. 2005, Oulu, Finland. [IEEE Xplore link]

[113] **R. B. Staszewski**, K. Muhammad, and D. Leipold, “Digital RF processor (DRP™) for cellular phones,”* Proc. of IEEE International Conf. on Computer Aided Design (ICCAD),* pp. 122–129, Nov. 2005, San Jose, CA, USA. [IEEE Xplore link]

[114] **R. B. Staszewski**, G. Shriki, and P. T. Balsara, “All-Digital PLL with Ultra Fast Acquisition” *Proc. of IEEE Asian Solid-State Circuits Conf. (ASSCC),* sec. 11–7, pp. 289–292, Nov. 2005, Taipei, Taiwan. [IEEE Xplore link]

[115] **R. B. Staszewski**, C.-M. Hung, and Y.-C. Ho, “RF amplitude control in an all-digital PLL based transmitter,” P*roc. of International SoC Design Conference (ISOCC), *sec. 12, pp. 203–206, Oct. 2005, Seoul, Korea.

[116] Y.-C. Ho, C.-M. Hung, K. Muhammad, C. Fernando, P. Cruise, **R. B. Staszewski**, D. Leipold, and K. Maggio, “A 1.8dB NF receiver front-end for GSM/GPRS in a 90nm digital CMOS,” *Proc. of International SoC Design Conference (ISOCC),* ses. 12, pp. 211–214, Oct. 2005, Seoul, Korea.

[117] **R. B. Staszewski** and R. Staszewski, “Interpolative pulse-shape filtering for a GSM/Bluetooth transmitter,” *Proc. of 2005 IEEE Dallas/CAS Workshop: Architectures, Circuits and Implementation of SoC (DCAS–05),* pp. 191–194, Oct. 2005, Dallas, TX, USA. [IEEE Xplore link]

[118] V. K. Parikh, G. Feygin, P. T. Balsara, S. Rezeq,**R. B. Staszewski**, S. Vemulapalli, and O. Eliezer, “Implementation of a high speed digital band-pass sigma-delta modulator for a wireless transmitter,” *Proc. of 2005 IEEE Dallas/CAS Workshop: Architectures, Circuits and Implementation of SoC (DCAS-05),* pp. 207–210, Oct. 2005, Dallas, TX, USA. [IEEE Xplore link]

[119] Y.-C. Ho, K. Muhammad, M.-C. Lee, C.-M. Hung, J. Wallberg, C. Fernando, P. Cruise, **R. B. Staszewski**, D. Leipold, and K. Maggio, “A GSM/GPRS receiver front-end with discrete-time filters in a 90 nm digital CMOS,” *Proc. of 2005 IEEE Dallas/CAS Workshop: Architectures, Circuits and Implementation of SoC (DCAS-05),* pp. 199–202, Oct. 2005, Dallas, TX, USA. [IEEE Xplore link]

[120] I. Bashir, **R. B. Staszewski**, O. Eliezer, and E. de-Obaldia, “Built-in self testing (BIST) of RF performance in a system-on-chip (SoC),” *Proc. of 2005 IEEE Dallas/CAS Workshop: Architectures, Circuits and Implementation of SoC (DCAS–05),* pp. 215–218, Oct. 2005, Dallas, TX, USA. [IEEE Xplore link]

[121] K. Waheed and **R. B. Staszewski**, “Characterization of deep-submicron varactor mismatches in a digitally controlled oscillator,” *Proc. of 2005 IEEE Custom Integrated Circuits Conf.,* sec. 18–3, pp. 605–608, Sept. 2005, San Jose, CA, USA. [IEEE Xplore link]

[122] K. Muhammad, Y.-C. Ho, T. Mayhugh, C.-M. Hung, T. Jung, I. Elahi, C. Lin, I. Deng, C. Fernando, J. Wallberg, S. Vemulapalli, S. Larson, T. Murphy, D. Leipold, P. Cruise, J. Jaehnig, M.-C. Lee, **R. B. Staszewski**, R. Staszewski, and K. Maggio, “A discrete time quad-band GSM/GPRS receiver in a 90nm digital CMOS process,” *Proc. of 2005 IEEE Custom Integrated Circuits Conf., *sec. 28–5, pp. 809–812, Sept. 2005, San Jose, CA, USA. [IEEE Xplore link]

[123] K. Waheed and **R. B. Staszewski**, “Time-domain behavioral modeling of a multigigahertz digital RF oscillator using VHDL,”* Proc. of IEEE Midwest Symp. on Circuits and Systems,* session C3L-B, pp. 1669-1672, Aug. 2005, Cincinnati, OH, USA. [IEEE Xplore link]

[124] K. Waheed and **R. B. Staszewski**, “Harmonic characterization of mismatches in deep sub-micron varactors for a digitally controlled RF oscillator,” *Proc. of IEEE Midwest Symp. on Circuits and Systems,* session B3L–G, pp. 951–954, Aug. 2005, Cincinnati, OH, USA. [IEEE Xplore link]

[125] **R. B. Staszewski**, R. Staszewski, and P. T. Balsara, “VHDL simulation and modeling of an all-digital RF transmitter,” *Proc. of IEEE Fifth Intl. Workshop on SoC for Real-Time Applications, *pp. 233–238, July 2005, Banff, Canada. [IEEE Xplore link]

[126] **R. B. Staszewski**, S. Rezeq, C.-M. Hung, P. Cruise, and J. Wallberg, “Sigma-delta noise shaping for digital-to-frequency and digital-to-RF-amplitude conversion,” *Proc. of IEEE Fifth Intl. Workshop on SoC for Real-Time Applications,* pp. 154–159, July 2005, Banff, Canada. [IEEE Xplore link]

[127] **R. B. Staszewski**, K. Muhammad, and D. Leipold, “Digital RF processing techniques for SoC radios (invited),” *Proc. of IEEE Fifth Intl. Workshop on SoC for Real-Time Applications,* pp. 217–222, July 2005, Banff, Canada. [IEEE Xplore link]

[128] C.-M. Hung, N. Barton, **R. B. Staszewski**, M.-C. Lee, and D. Leipold, “A first RF digitally-controlled oscillator for SAW-less TX in cellular systems,” *Proc. of 2005 IEEE Symp. on VLSI Circuits,* sec. 25.3, pp. 402–405, June 2005, Kyoto, Japan. [IEEE Xplore link]

[129] **R. B. Staszewski**, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, “Time-to-digital converter for RF frequency synthesis in 90 nm CMOS,” *Proc. of 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., *sec. RTU3B–4, pp. 473–476, June 2005, Long Beach, CA, USA. [IEEE Xplore link]

[130] **R. B. Staszewski**, C.-M. Hung, N. Barton, M.-C. Lee, and D. Leipold, “A first RF digitally-controlled oscillator for mobile phones,” *Proc. of 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., *sec. RMO2B–1, pp. 119–122, June 2005, Long Beach, CA, USA. [IEEE Xplore link]

[131] P. Cruise, C.-M. Hung, **R. B. Staszewski**, O. Eliezer, S. Rezeq, D. Leipold, and K. Maggio, “A digital-to-RF-amplitude converter for GSM/GPRS/EDGE in 90-nm digital CMOS,” *Proc. of 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symp.,* sec. RMO1A–4, pp. 21–24, June 2005, Long Beach, CA, USA.[IEEE Xplore link]

[132] **R. B. Staszewski**, J. Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, “ All-digital PLL and GSM/EDGE transmitter in 90nm CMOS,” *Proc. of IEEE Solid-State Circuits Conf.,* sec. 17.5, pp. 316–317, 600, Feb. 2005, San Francisco, CA, USA. [IEEE Xplore link]

#### 2004

[133] J. Koh, K. Muhammad, **B. Staszewski**, G. Gomez, and B. Horoun, “ A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process,” *Proc. of 2004 IEEE Custom Integrated Circuits Conf., *sec. 25–6, pp. 535–538, Oct. 2004, Orlando, FL, USA. [IEEE Xplore link]

[134] **R. B. Staszewski**, J. Wallberg, and J. Koh, “High-speed digital circuits for a 2.4 GHz all-digital RF frequency synthesizer in 130 nm CMOS,” *Proc. of 2004 IEEE Dallas CAS Workshop: Implementation of High Performance Circuits, *pp. 167–170, Sept. 2004, Dallas, TX, USA.[IEEE Xplore link]

[135] **R. B. Staszewski**, R. Staszewski, J. Wallberg, T. Jung, C.-M. Hung, D. Leipold, K. Maggio, and P. T. Balsara, “DSP-coupled 2.4 GHz RF transmitter in 130 nm CMOS,” *Proc. of 2004 IEEE Dallas CAS Workshop: Implementation of High Performance Circuits,* pp. 163–166, Sept. 2004, Dallas, TX, USA. [IEEE Xplore link]

[136] **R. B. Staszewski**, D. Leipold, C.-M. Hung, and P. T. Balsara, “TDC-based frequency synthesizer for wireless applications,” *Proc. of 2004 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., *sec. MO2D–3, pp. 215–218, June 2004, Fort Worth, TX, USA. [IEEE Xplore link]

[137] K. Muhammad, **R. B. Staszewski**, and C.-M. Hung, “Joint common mode voltage and differential offset voltage control scheme in a low-IF receiver,” *Proc. of 2004 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., *sec. TU3C–2, pp. 405–408, June 2004, Fort Worth, TX, USA. [IEEE Xplore link]

[138] **R. B. Staszewski**, C. Fernando, and P. T. Balsara, “Event-driven simulation and modeling of an RF oscillator,”* Proc. of 2004 IEEE Intl. Symp. on Circuits and Systems,* sec. NLCS–L6.3, pp. IV–641–IV–644, May 2004, Vancouver, Canada. [IEEE Xplore link]

[139] K. Muhammad and **R. B. Staszewski**, “Direct RF sampling mixer with recursive filtering in charge domain,” *Proc. of 2004 IEEE Intl. Symp. on Circuits and Systems, *sec. ASP–L29.5, pp. I–577–I–580, May 2004, Vancouver, Canada. [IEEE Xplore link]

[140] **B. Staszewski**, C.-M. Hung, K. Maggio, J. Wallberg, D. Leipold, and P. Balsara, “All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13µm CMOS,” *Proc. of IEEE Solid-State Circuits Conf., *sec. 15.3, pp. 272–273, 527, Feb. 2004, San Francisco, CA, USA. [IEEE Xplore link]

[141] K. Muhammad, D. Leipold,**B. Staszewski**, Y.-C. Ho, C.-M. Hung, K. Maggio, C. Fernando, T. Jung, J. Wallberg, J.-S. Koh, S. John, I. Deng, O. Moreira, R. Staszewski, R. Katz, and O. Friedman, “A discrete-time Bluetooth receiver in a 0.13µm digital CMOS process,” *Proc. of IEEE Solid-State Circuits Conf., *sec. 15.1, pp. 268–269, 527, Feb. 2004, San Francisco, CA, USA. [IEEE Xplore link]

#### 2003

[142] **R. B. Staszewski**, D. Leipold, J. Wallberg, and P. T. Balsara, “Just-in-time gain estimation of an RF digitally-controlled oscillator,” * Proc. of 2003 IEEE Custom Integrated Circuits Conf., *sec. 25–8, pp. 571–574, Sept. 2003, San Jose, CA, USA. [IEEE Xplore link]

[143] **R. B. Staszewski**, D. Leipold, C.-M. Hung, and P. T. Balsara, “A first digitally-controlled oscillator in a deep-submicron CMOS process for multi-GHz wireless applications,” *Proc. of 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., *sec. MO4B–2, pp. 81–84, June 2003, Philadelphia, PA, USA. [IEEE Xplore link]

#### 2001

[144] K. Muhammad,**R. B. Staszewski**, and P. T. Balsara, “Challenges in integrated CMOS transceivers for short distance wireless,” *Proc. of 11th Great Lakes Symposium on VLSI, *pp. 45–50, 22–23 Mar. 2001, (invited paper), Chicago, IL, USA.

#### 2000

[145] **R. B. Staszewski**, K. Muhammad, and P. Balsara, “A constrained asymmetry LMS algorithm for PRML disk drive read channels,” Proc. of the 34th Asilomar Conf. On Signals, *Systems and Computers, *sec. MP6a.3, pp. 433–437, Nov. 2000, Pacific Grove, CA, USA. [IEEE Xplore link]

[146] K. Muhammad, **R. B. Staszewski**, and P. T. Balsara, “Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels,”* Proc. of IEEE International Symposium on Low Power Electronics and Design,* sec. 9.2, pp. 262–267, July 2000, Rapallo, Italy. [IEEE Xplore link]

[147] **R. B. Staszewski**, K. Muhammad, and P. Balsara, “A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels,” *Proc. of IEEE Solid-State Circuits Conf., sec. MP4.7,* pp. 80–81, Feb. 2000, San Francisco, CA, USA. [IEEE Xplore link]

#### 1999

[148] **R. B. Staszewski** and S. Kiriaki, “Top-down simulation methodology of a 500 MHz mixed-signal magnetic recording read channel using standard VHDL,” *Proc. of Behavioral Modeling and Simulation Conf., *sec. 3.2, Oct. 1999, Orlando, FL, USA.

#### 1997

[149] G. Feygin, **B. Staszewski**, and S. Kiriaki, “Area and power efficient implementation of LMS adaptive equalization for an analog PRML read channel,” *Proc. of EE-Times Analog and Mixed-Signal Applications Conf.,* sec. 2C, pp. 229–234, July 1997, San Jose, CA, USA.

[150] S. Kiriaki, T. L. Viswanathan, G. Feygin, **B. Staszewski**, R. Pierson, B. Krenik, M. de Wit, and K. Nagaraj, “A 160-MHz analog equalizer for magnetic disk read channels,” *Proc. of IEEE Solid-State Circuits Conf., *sec. SA19.5, pp. 322–323, 479, Feb. 1997, San Francisco, CA, USA. [IEEE Xplore link]