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Issued US Patents: Accessed from http://patft.uspto.gov/



2015

TIME-TO-DIGITAL SYSTEM AND ASSOCIATED FREQUENCY SYNTHESIZER

LINEARIZATION AND CALIBRATION PREDISTORTION OF A DIGITALLY CONTROLLED POWER AMPLIFIER

HIGH-IF SUPERHETERODYNE RECEIVER INCORPORATING HIGH-Q COMPLEX BAND PASS FILTER

FREQUENCY MODULATOR HAVING DIGITALLY-CONTROLLED OSCILLATOR WITH MODULATION TUNING AND PHASE-LOCKED LOOP TUNING

POLAR TRANSMITTER HAVING FREQUENCY MODULATING PATH WITH INTERPOLATION IN COMPENSATING FEED INPUT AND RELATED METHOD THEREOF

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2014

PHASE LOCKED LOOP(PLL) WITH MUTI-PHASE TIME-TO-DIGITAL CONVERTER TDC

OSCILLATOR CIRCUIT AND METHOD FOR GENERATING AN OSCILLATION

APPARATUS AND METHOD FOR CALIBRATING TIMING MISMATCH OF EDGE ROTATOR OPERATING ON MULTIPLE PHASES OF OSCILLATOR

POLAR TRANSMITTER HAVING DIGITAL PROCESSING BLOCK USED FOR ADJUSTING FREQUENCY MODULATING SIGNAL FOR FREQUENCY DEVIATION OF FREQUENCY MODULATED CLOCK AND RELATED METHOD THEREOF

DIGITALLY-CONTROLLED POWER AMPLIFIER WITH BANDPASS FILTERING/TRANSIENT WAVEFORM CONTROL AND RELATED DIGITALLY-CONTROLLED POWER AMPLIFIER CELL

FREQUENCY SYNTHESIZER AND ASSOCIATED METHOD

TRANSMITTER EMPLOYING PULLING MITIGATION MECHANSIM AND RELATED METHOD THEREOF

DIGITAL AMPLITUDE MODULATION

INTEGRATED CIRCUIT, COMMUNICATION UNIT AND METHOD FOR IMPROVED AMPLITUDE RESOLUTION OF AN RF-DAC

LOW POWER ALL DIGITAL PLL ARCHITECTURE

DIGITAL PHASE LOCKED LOOP

METHOD AND APPARATUS OF ESTIMATING/CALIBRATING TDC MISMATCH

TRANSMITTER AND FREQUENCY DEVIATION REDUCTION METHOD THEREOF

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2013

MULTI-STAGE DIGITALLY-CONTROLLED POWER AMPLIFIER

PHASE LOCKED LOOP (PLL) WITH MULTI-PHASE TIME-TO-DIGITAL CONVERTER (TDC)

FREQUENCY SYNTHESIZER AND ASSOCIATED METHOD

PVT-FREE CALIBRATION CIRCUIT FOR TDC RESOLUTION IN ADPLL

CLOCK GENERATOR FOR GENERATING OUTPUT CLOCK HAVING NONHARMONIC RELATIONSHIP WITH INPUT CLOCK AND RELATED CLOCK GENERATING METHOD THEREOF-I

All-DIGITAL FREQUENCY SYNSTHESIS WITH DCO GAIN CALCULATION

SIMULTANEOUS MULTIPLE SIGNAL RECEPTION AND TRANSMISSION USING FREQUENCY MULTIPLEXING AND SHARED PROCESSING

CLOCK GENERATOR FOR GENERATING OUTPUT CLOCK HAVING NONHARMONIC RELATIONSHIP WITH INPUT CLOCK AND RELATED CLOCK GENERATING METHOD THEREOF-II

PREDISTORTION CALIBRATION AND BUILT IN SELF TESTING OF A RADIO FREQUENCY POWER AMPLIFIER USING SUBHARMONIC MIXING

DIGITAL AMPLITUDE MODULATION

DIGITAL PHASE LOCKED LOOP

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2012

METHOD AND APPARATUS FOR ASYNCHONOUS CLOCK RETIMING

LINEARIZATION OF A TRANSMIT AMPLIFIER

RADIO FREQUENCY BUILT-IN SELF TEST

BANDWIDTH REDUCTION MECHANISM FOR POLAR MODULATION

COMPUTATION SPREADING UTILIZING DITHERING FOR SPUR REDUCTION IN A DIGITAL PHASE LOCK LOOP

POWER AMPLIFIER WITH TWO TRANSISTORS AND TRACES FORMING TWO TRANSFORMERS

TRANSMITTER PLL WITH BANDWIDTH ON DEMAND

LOCAL OSCILLATOR WITH NON-HARMONIC RATIO BETWEEN OSCILLATOR AND RF ..

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2011

DIGITAL PHASE LOCKED LOOP WITH INTEGER CHANNEL MITIGATION

BINARY RIPPLE COUNTER SAMPLING WITH ADJUSTABLE DELAYS

INTERPOLATIVE ALL-DIGITAL PHASE LOCKED LOOP

SAMPLING MIXER WITH ASYNCHRONOUS CLOCK AND SIGNAL DOMAINS

PARALLEL REDUNDANT SINGLE-ELECTRON DEVICE AND METHOD OF MANUFACTURE

REMOVING CLOSE-IN INTERFERERS THROUGH A FEEDBACK LOOP

ALL-DIGITAL FREQUENCY SYNTHESIS WITH DCO GAIN CALCULATION

VARIABLE DELAY OSCILLATOR BUFFER

ON-CHIP RECEIVER SENSITIVITY TEST MECHANISM

COMPUTATION SPREADING FOR SPUR REDUCTION IN A DIGITAL PHASE LOCK LOOP

LOCAL OSCILLATOR INCORPORATING PHASE COMMAND EXCEPTION HANDLING UTILIZING A QUADRATURE SWITCH

METHOD AND APPARATUS FOR DIGITAL AMPLITUDE AND PHASE MODULATION

DIGITAL PHASE LOCKED LOOP WITH DITHERING

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2010

POWER AMPLIFIER

RECISE DELAY ALIGNMENT BETWEEN AMPLITUDE AND PHASEIFREQUENCY MODULATION PATHS IN A DIGITAL POLAR TRANSMITTER

METHOD OF DEFINING SEMICONDUCTOR FABRICATION PROCESS UTILIZING TRANSISTOR INVERTER DELAY PERIOD

COMPUTATION PARALLELIZATION IN SOFTWARE RECONFIGURABLE ALL DIGITAL PHASE LOCK LOOP

ALL DIGITAL PHASE LOCKED LOOP ARCHITECTURE FOR POWER CELLULAR APPLICATIONS

TECHIQUE FOR IMPROVING ANTIALIASING AND DJACENT CHANNEL INTERFERENCE FILTERING USINGG CASCADED PASSIVE IIR FILTER STAGES COMBINIED WITH DIRECT SAMPLING AND MIXING

DIGITAL PHASE LOCKED LOOP WITH DITHERING

TRANSMITTER FOR WIRELESS APPLICATIONS INCORPORATION SPECTRAL EMISSION SHAPING SIGMA DELTA MODULATOR

LOCAL OSCILLATOR WITH NON-HARMONIC RATIO BETWEEN OSCILLATOR AND RF FREQUENCIES USING XOR OPERATION WITH JITTER ESTIMATION AND CORRECTION

DIGITAL PHASE LOCKED LOOP WITH GEAR SHIFTING

INTEGRATED POWER AMPLIFIER

SINGLE-ELECTRON TUNNEL JUNCTION FOR COMPLEMENTARY METAL-OXIDE DEVICE AND METHOD OF MANUFACTURING THE SAME

LOCAL OSCILLATOR WITH NON-HARMONIC RATIO BETWEEN OSCILLATOR AND RF FREQUENCIES USING PULSE GENERATION AND SELECTION

APPARATUS AND METHOD FOR ACQUISITION AND TRACKING BANK COOPERATION IN A DIGITALLY CONTROLLED OSCILLATOR

HARMONIC CHARACTERIZATION AND CORRECTION OF DEVICE MISMATCH

FAST HOPPING FREQUENCY SYNTHESIZER USING AN ALL DIGITAL PHASED LOCKED LOOP (ADPLL)

OSCILLATOR SYSTEM, METHOD OF PROVIDING A RESONATING SIGNAL AND A COMMUNICATIONS SYSTEM EMPLOYING THE SAME

HYBRID STOCHASTIC GRADIENT BASED DIGITALLY CONTROLLED OSCILLATOR GAIN KDCO ESTIMATION

EFFICIENT PULSE AMPLITUDE MODULATION TRANSMIT MODULATION

ACTIVE REMOVAL OF ALIASING FREQUENCIES IN A DECIMATING STRUCTURE BY CHANGING A DECIMATION RATIO IN TIME AND SPACE

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2009

SAMPLING MIXER WITH ASYNCHRONOUS CLOCK AND SIGNAL DOMAINS

CALIBRATION CIRCUITRY AND DELAY CELLS IN RECTILINEAR RF POWER AMPLIFIER

ADAPTIVE SPECTRAL NOISE SHAPING TO IMPROVE TIME TO DIGITAL CONVERTER QUANTIZATION RESOLUTION USING DITHERING

SINGLE-ELECTRON INJECTIONIEXTRACTION DEVICE FORA RESONANT TANK CIRCUIT AND METHOD OF OPERATION THEREOF

PREDISTORTION CALIBRATION IN A TRANSCEIVER ASSEMBLY

HYBRID POLAR/CARTESIAN DIGITAL MODULATOR

DIRECT RADIO FREQUENCY (RF) SAMPLING WITH RECURSIVE FILTERING METHOD

CONTINUOUS REVERSIBLE GEAR SHIFTING MECHANISM

GAIN NORMALIZATION OF A DIGITALLY CONTROLLED OSCILLATOR IN AN ALL DIGITAL PHASE LOCKED LOOP BASED TRANSMITTER

ALL-DIGITAL FREQUENCY SYNTHESIS WITH NON-LINEAR DIFFERENTIAL TERM FOR HANDLING FREQUENCY PERTURBATIONS

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2008

ACTIVE REMOVAL OF ALIASING FREQUENCIES IN A DECIMATING STRUCTURE BY CHANGING A DECIMATION RATIO IN TIME AND SPACE

GAIN CALIBRATION OF A DIGITAL CONTROLLED OSCILLATOR

LOW NOISE HIGH ISOLATION TRANSMIT BUFFER GAIN CONTROL MECHANISM

WIRELESS COMMUNICATIONS DEVICE HAVING TYPE-II ALL-DIGITAL PHASE-LOCKED LOOP (PLL)

MODULATION NOISE ESTIMATION MECHANISM

METHOD AND APPARATUS FORA FULLY DIGITAL QUADRATURE MODULATOR

FREQUENCY TUNING RANGE EXTENSION AND MODULATION RESOLUTION ENHANCEMENT OF A DIGITALLY CONTROLLED OSCILLATOR

TRANSMIT FILTER

TIME-TO-DIGITAL CONVERTER WITH NON-INVERTING BUFFERS, TRANSMISSION GATES AND NON-LINEARITY CORRECTOR, SOC INCLUDING SUCH CONVERTERAND METHOD OF PHASE DETECTION FOR USE IN SYNTHESIZINGA CLOCK SIGNAL

TECHNIQUE FOR IMPROVING ANTIALIASING AND ADJACENT CHANNEL INTERFERENCE FILTERING USING CASCADED PASSIVE IIR FILTER STAGES COMBINED WITH DIRECT SAMPLINGAND MIXING

BUILT-IN SELF TEST METHOD FORA DIGITALLY CONTROLLED CRYSTAL OSCILLATOR

NEGATIVE CONTRIBUTIVE OFFSET COMPENSATION IN A TRANSMIT BUFFER UTILIZING INVERSE CLOCKING

TYPE-II ALL-DIGITAL PHASE-LOCKED LOOP (PLL)

HYBRID STOCHASTIC GRADIENT BASED DIGITALLY CONTROLLED OSCILLATOR GAIN Kdco ESTIMATION

OSCILLATOR SYSTEM, METHOD OF PROVIDING A RESONATING SIGNAL AND A COMMUNICATIONS SYSTEM EMPLOYING THE SAME

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2007

CIRCUIT FOR HIGH-RESOLUTION PHASE DETECTION IN A DIGITAL RF PROCESSOR

ON-CHIP RECEIVER SENSITIVITY TEST MECHANISM

REMOVING CLOSE-IN INTERFERERS THROUGH A FEEDBACK LOOP

GAIN CALIBRATION OF A DIGITAL CONTROLLED OSCILLATOR

FAST HOPPING FREQUENCY SYNTHESIZER USING AN ALL DIGITAL PHASED LOCKED LOOP (ADPLL)

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2006

SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER (ADC) STRUCTURE INCORPORATING A DIRECT SAMPLING MIXER

EFFICIENT CHARGE TRANSFER USING A SWITCHED CAPACITOR RESISTOR

ALL-DIGITAL FREQUENCY SYNTHESIS WITH CAPACITIVE RE-INTRODUCTION OF DITHERED TUNING INFORMATION

FREQUENCY SYNTHESIZER WITH PHASE RESTART

ACTIVE REMOVAL OF ALIASING FREQUENCIES IN A DECIMATING STRUCTURE BY CHANGING A DECIMATION RATIO IN TIME AND SPACE

TYPE-II ALL-DIGITAL PHASE-LOCKED LOOP (PLL)

METHOD AND ARCHITECTURE FOR CONTROLLING ASYMMETRY OF AN LMS ADAPTATION ALGORITHM THAT CONTROLS FIR FILTER COEFFICIENTS

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2005

EFFICIENT PULSE AMPLITUDE MODULATION TRANSMIT MODULATION

ACTIVE REMOVAL OF ALIASING FREQUENCIES IN A DECIMATING STRUCTURE BY CHANGING A DECIMATION RATIO IN TIME AND SPACE

MULTI-TAP, DIGITAL-PULSE-DRIVEN MIXER

DIGITAL PLL WITH GEAR SHIFT

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2004

PHYBRID OF PREDICTIVE AND CLOSEDLOOP PHASE-DOMAIN DIGITAL PLL ARCHITECTURE

FREQUENCY SYNTHESIZER WITH DIGITALLY-CONTROLLED OSCILLATOR

FREQUENCY SYNTHESIZER WITH DIGITALLY-CONTROLLED OSCILLATOR

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2003

DIGITALLY-CONTROLLED L-C OSCILLATOR

POWER SAVING CIRCUITRY USING PREDICTIVE LOGIC

SYSTEM AND METHOD FOR TIME DITHERING A DIGITALLY-CONTROLLED OSCILLATOR TUNING INPUT

HIGH-SPEED DIGITAL TIMING AND GAIN GRADIENT CIRCUIT EMPLOYING A PARALLELARCHITECTURE

METHOD AND ARCHITECTURE FOR CONTROLLING ASYMMETRY OF AN LMS ADAPTATION ALGORITHM THAT CONTROLS FIR FILTER COEFFICIENTS

METHOD AND ARCHITECTURE TO FACILITATE ACHIEVING A FAST EPR4 EQUALIZATION START-UP IN A MAGNETIC RECORDINGREADCHANNEL

PHASE DETECTOR ARCHITECTURE FOR PHASE ERROR ESTIMATING AND ZERO PHASE RESTARTING

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2002

DIGITAL FRACTIONAL PHASE DETECTOR

FREQUENCY SYNTHESIZER

PHASE-SHIFT CALCULATION METHOD, AND SYSTEM IMPLEMENTING IT, FOR A FINITE-IMPULSE-RESPONSE (FIR) FILTER

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2001

DIGITAL PHASE-DOMAIN PLL FREQUENCY SYNTHESIZER

METHOD AND SYSTEM FOR ESTIMATING AN INPUT DATA SEQUENCE BASED ON AN OUTPUT DATA SEQUENCE AND HARD DISK DRIVE INCORPORATING SAME

HIGH-SPEED DIGITAL CIRCUIT EMPLOYING A BAND-ZERO-DETERMINATION-ASIDE (B0DA) ARCHITECTURE

DIGITAL FINITE-IMPULSE-RESPONSE (FIR) FILTER WITH A MODIFIED ARCHITECTURE BASED ON HIGH ORDER RADIX-N NUMBERING

METHOD AND APPARATUS FOR ACQUIRING A PREAMBLE SIGNAL IN A HARD DISK DRIVE

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2000

METHOD AND APPARATUS FOR EXTRACTING BAND AND ERROR VALUES FROM DIGITAL SAMPLES OF AN ANALOG SIGNAL

1999

SYNC DETECT CIRCUIT

1996

HIGH FREQUENCY TRANSFORMER APPARATUS

1994

PHASE DETECTOR AND METHODOLOGY

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