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Our team researches and develops IC chips for frequency synthesis and wireless communications. We design RF, wireless transceivers, all-digital I/Q modulator, digital pre PA for cellular basestations, mm-wave and mixed-signal circuits:

Our Published Projects



babaie-pic "Ultra-Low Phase Noise 7.2-8.7 GHz Clip-and-Restore Oscillator with 191 dBc/Hz"

Research lead: Masoud Babaie. In this reseach work we have proposed a new class of operation of an RF oscillator that minimizes its phase noise. The main idea is to enforce a clipped voltage waveform around the LC tank by increasing the second-harmonic of fundamental oscillation voltage through an additional impedance peak, thus giving rise to a class-F2 operation. As a result, the noise contribution of the tail current transistor on the total phase noise can be significantly decreased without sacrificing the oscillator's voltage and current efficiencies. Furthermore, its special impulse sensitivity function(ISF) reduces the phase sensitivity to thermal circuit noise. The prototype of the class-F2 oscillator is implemented in standard TSMC 65 nm CMOS occupying 0.2 mm2. It draws 32–38 mA from 1.3 V supply. Its tuning range is 19% covering 7.2–8.8 GHz. It exhibits phase noise of 139 dBc/Hz at 3 MHz offset from 8.7 GHz carrier, translated to an average figure-of-merit of 191 dBc/Hz with less than 2 dB variation across the tuning range. The long term reliability is also investigated with estimated >10 year lifetime [IEEE Xplore link (Open Access)] [IEEE Xplore link][IEEE Xplore link] .



tohidian-pic "Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter"

Research lead: Massoud Tohidian. A discrete-time IIR low-pass filter that achieves a high-order of filtering through a charge-sharing rotation. Its sampling rate is then multiplied through pipelining. The first stage of the filter can operate in either a voltage-sampling or charge-sampling mode. It uses switches, capacitors and a simple gm-cell, rather than opamps, thus being compatible with digital nanoscale technology. In the voltage-sampling mode, the gm-cell is bypassed so the filter is fully passive. A 7th-order filter prototype operating at 800 MS/s sampling rate is implemented in TSMC 65 nm CMOS. Bandwidth of this filter is programmable between 400 kHz to 30 MHz with 100 dB maximum stop-band rejection. Its IIP3 is +21 dBm and the averaged spot noise is 4.57 nV. [IEEE Xplore link (Open Access)] [IEEE Xplore link]



wanghua-pic "A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS"

Research lead: Dr. Wanghua Wu. A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. The fractional-N ADPLL employs a high-resolution 60 GHz digitallycontrolled oscillator (DCO) and is capable of multi-rate two-point FM. It achieves a measured rms jitter of 590.2 fs, while the loop settles within 3 µs. The measured reference spur is only –74 dBc, the fractional spurs are below –62 dBc, with no other significant spurs. A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multiple DCO tuning banks with a measured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHzrms for a 62 GHz carrier with 1.22 GHz bandwidth. The synthesizer is transformer-coupled to a 3-stage neutralized power amplifier (PA) that delivers +5 dBm to a 50 O load. Implemented in 65 nm CMOS, the transmitter prototype (including PA) consumes 89 mW from a 1.2 V supply. This project is funded by STW in phase I. [IEEE Xplore link (Open Access)]



jssc_wu_mm-dco-pic "High-Resolution Millimeter-Wave Digitally Controlled Oscillators With Reconfigurable Passive Resonators"

Research lead: Dr. Wanghua Wu. Two new millimeter-wave digitally controlled oscillators (DCOs) that achieve a tuning range 10% and fine frequency resolution 1 MHz simultaneously are described. Switched metal capacitors distributed across a passive resonator tune the oscillation frequency. To obtain sub-MHz frequency resolution, tuning step attenuation techniques exploiting an inductor and a transformer are proposed. Two 60-GHz implementations, a fine-resolution inductor-based DCO (L-DCO) and a transformer-coupled DCO (T-DCO), are demonstrated in 90-nm CMOS. The phase noise of both DCOs is lower than 90.5 dBc/Hzat 1-MHz offset across 56–62 GHz. The T-DCO achieves a fine frequency tuning step of 2.5 MHz, whereas the L-DCO tuning step is over one order of magnitude finer at 160 kHz. The L-DCO and T-DCO consume 10 and 12 mA, respectively, from a 1.2-V supply. The size of each DCO core is 0.4 0.4 mm2 [IEEE Xplore link].



iq-pic "A Wideband 2 13-bit All-Digital I/Q RF-DAC"

Research lead: Dr. Morteza Alavi. This research work proposes a wideband 2x13-bit in-phase/quadrature-phase (I/Q) RF digital-to-analog converter-based alldigital modulator realized in 65-nm CMOS. The isolation between I and Q paths is guaranteed employing 25% duty-cycle differential quadrature clocks. With a 1.3-V supply and an on-chip power combiner, the digital I/Q transmitter provides more than 21-dBm RF output power within a frequency range of 1.36–2.51 GHz. The peak RF output power, overall system, and drain efficiencies of the modulator are 22.8 dBm, 34%, and 42%, respectively. The measured static noise floor is below 160 dBc/Hz. The digital I/Q RF modulator demonstrates an IQ image rejection and local oscillator leakage of 65 and 68 dBc, respectively. It could be linearized using either of the two digital predistortion (DPD) approaches: a memoryless polynomial or a lookup table. Its linearity is examined using single-carrier 4/16/64/256/1024 quadrature amplitude modulation(QAM), as well as multi-carrier 256-QAM orthogonal frequency division multiplexing baseband signals while their related modulation bandwidth can be as high as 154 MHz. Employing DPD improves the third-order intermodulation product (IM 3) by more than 25 dB, while the measured error vector magnitude for a “single-carrier 22-MHz 64-QAM” signal is better than 28 dB. This project is funded by STW in both phase I & II. [IEEE Xplore link (Open Access)]



visweswaran-pic

"A Low Phase Noise Oscillator Principled on Transformer-Coupled Hard Limiting"

Research lead: Akshay Visweswaran. Reduced phase noise conversion in a monolithic oscillator suitable for basestation applications is realized by hard limiting and subsequently restoring the resonating waveform. Overdriven transistors hard limit the drain voltage swing and it is shown analytically that this desensitizes the oscillation phase to circuit noise. A pair of tuned, 1:2 step-up transformers in the feedback path restore the fundamental frequency component with sufficient gain to overdrive the transistors forming the oscillator core, with greater selectivity than an equivalent LC tank. The 8 GHz, 65 nm CMOS oscillator prototype targeting the GSM-900 base-station specification consumes 32 mA from 1.5 V. Normal-ized to 915 MHz, the phase noise measured at 1 MHz offset is –147.7 dBc/Hz, validating predictions from theory and simulation. The measured frequency pushing is less than 16 MHz/V [IEEE Xplore link].



babaie-pic"A Class-F CMOS Oscillator"

Research lead: Masoud Babaie. An oscillator topology demonstrating an improved phase noise performance is proposed in this paper. It exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The proposed oscillator is based on enforcing a pseudo-square voltage waveform around the LC tank by increasing the third-harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled resonating windings. As a result, the effective impulse sensitivity function (ISF) decreases thus reducing the oscillator’s effective noise factor such that a significant improvement in the oscillator phase noise and power efficiency are achieved. A com-prehensive study of circuit-to-phase-noise conversion mechanisms of different oscillators’ structures shows the proposed class-F exhibits the lowest phase noise at the same tank’s quality factor and supply voltage. The prototype of the class-F oscillator is im- plemented in TSMC 65-nm standard CMOS. It exhibits average phase noise of 136 dBc/Hz at 3 MHz offset from the carrier over 5.9–7.6 GHz tuning range with figure-of-merit of 192 dBc/Hz. The oscillator occupies 0.12 mm while drawing 12 mA from 1.25 V supply. [IEEE Xplore link (Open Access)] .



tohidian-pic "Dual-Core High-Swing Class-C Oscillator with Ultra-Low Phase Noise"

Research lead: Massoud Tohidian. An ultra-low phase noise oscillator is proposed. The basis of the proposed idea is that coupling a second oscillator core reduces the overall phase noise by 3 dB. For each core, a high-swing class-C oscillator is used to have the lowest phase noise. The oscillator is tunable from 4.07-4.91 GHz, drawing 39-59 mA from a 2.15 V power supply. The measured phase noise is -146.7 dBc/Hz and -163.1 dBc/Hz at 3 MHz and 20 MHz offset from a 4.07 GHz carrier, respectively. This is the lowest ever reported phase noise in bulk CMOS IC. This phase noise meets GSM900 normal basestation receiver and mobile station transmitter standards, which have the toughest phase noise requirements in cellular communications. [IEEE Xplore link]



madadi-pic "A 65nm CMOS High-IF Superheterodyne Receiver with a High-Q Complex BPF"

Research lead: Iman Madadi. A highly reconfigurable superheterodyne receiver that employs a 3rd-order complex IQ charge-sharing band-pass filter (BPF) for image rejection and 1st-order feedback based RF-BPF for channel selection filtering. The operating RF input frequency of the receiver is 500 MHz—1.4 GHz with varying high-IF range of 33—93 MHz. All the gain stages are merely inverter-based gm stages. The total gain of the receiver is 35 dB and in-band IIP3 at mid-gain is +10 dBm. The NF of the receiver is 6.7 dB, which is acceptable for the receiver without an LNA. The architecture is highly reconfigurable and follows the technology scaling. The RX occupies 0.47mm2 of active area and consumes 24.5mA at 1.2V power supply [IEEE Xplore link] .



 mehrpoo-pic "A Highly Selective LNTA Capable of Large-Signal Handling for RF Receiver Front-Ends"

Research lead: Mohammadreza Mehrpoo. To achieve ultimately flexible multi-core radio operation, wide-band receiver RF front-ends must be robust against interference well in excess of the requirements usually specified by a radio standard. In this paper, a highly selective, very linear low-noise transconductance amplifier (LNTA) capable of large-signal handling for current-mode receiver (RX) front-ends is proposed and implemented in 65-nm CMOS. It is shown that by combining on-chip high-Q bandpass filters with a push/pull class-AB common-gate stage, a measured 1-dB desensitization point (B1dB) and large-signal IIP3 of +8 dBm and +20 dBm, respectively, can be achieved. In addition, by applying a noise cancellation technique, via an auxiliary push/pull class-AB commonsource stage, the proposed LNTA measures a moderate NF of 5.9 dB, which is a very competitive number for such high value of B1dB. The circuit consumes 7.5 mA at 1.5 V [IEEE Xplore link].



Amir-pic "Frequency Translation through Fractional Divider for Two-Channel Pulling Mitigation"

Research lead: Amir Reza Ahmadi Mehr. A two-channel RF generation system for a 2 GHz basestation transmitter that avoids pulling due to various parasitic coupling paths, especially between a strong RF output and an LC-tank of an RF oscillator. This is achieved through a fractional frequency translation by means of a programmable fractional divider realized as a dynamic edge selector of eight oscillator phases. This way, the integer harmonic frequency relationship of victims/aggressors within and between the RF transmission channels are avoided, thus rendered harmless in the creation of injection pulling spurs. The proposed method can reduce the injection pulling spur to -99 dBc and has been verified in a 65-nm CMOS testchip that occupies 0.561.46 mm2 area and emits -156 dBc/Hz noise floor. An RF oscillator is realized as a class-C topology without the bias current source [IEEE Xplore link].



3D-pic "Time-of-Flight 3D Imager Realized as System-on-Chip (SoC)"

Research lead: Priyanka Kumar. Although 3D imaging techniques have existed for several decades, it has been mostly restricted to the research domain and high-cost low-volume applications. Stereoscopic (a set of two) 2D sensors have been mostly used due to low cost and short acquisition time. In most real-life situations though, true 3D imaging (with active illumination of the target instead of passive treatment of differences in perspective between two 2D sensors) is the only effective way for acquiring non-ambiguous 3D data. Unfortunately, the power consumption, cost and image acquisition speed are currently still severe roadblocks for 3D imagers and hamper their applications. This project is funded by STW in both phase I & II[IEEE Xplore link].

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